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COM Express Module Base Specification-R3.0
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COM Express Module Base Specification COM Express Module Base Specification COM Express Module Base Specification COM Express Module Base Specification
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COM Express®
Carrier Design Guide
Guidelines for designing COM Express® Carrier Boards
December 6, 2013
Rev. 2.0
This design guide is not a specification. It contains additional detail information but does not replace
the PICMG COM Express® (COM.0) specification.
For complete guidelines on the design of COM Express® compliant Carrier Boards and systems,
refer also to the full specification – do not use this design guide as the only reference for any design
decisions. This design guide is to be used in conjunction with COM.0 R2.1.
PICMG
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COM Express
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Carrier Board Design Guide Rev. 2.0 / December 6, 2013
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© Copyright 2013, PCI Industrial Computer Manufacturers Group. The attention of adopters is
directed to the possibility that compliance with or adoption of PICMG® specifications may require
use of an invention covered by patent rights. PICMG® shall not be responsible for identifying
patents for which a license may be required by any PICMG® specification or for conducting legal
inquiries into the legal validity or scope of those patents that are brought to its attention.
PICMG® specifications are prospective and advisory only. Prospective users are responsible for
protecting themselves against liability for infringement of patents.
NOTICE:
The information contained in this document is subject to change without notice. The material in
this document details a PICMG® specification in accordance with the license and notices set
forth on this page. This document does not represent a commitment to implement any portion of
this specification in any company's products.
WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE,
PICMG® MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO
THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF TITLE OR
OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS
FOR PARTICULAR PURPOSE OR USE.
In no event shall PICMG® be liable for errors contained herein or for indirect, incidental, special,
consequential, reliance or cover damages, including loss of profits, revenue, data or use,
incurred by any user or any third party. Compliance with this specification does not absolve
manufacturers of equipment from the requirements of safety and regulatory agencies (UL, CSA,
FCC, IEC, etc.).
IMPORTANT NOTICE:
This document includes references to specifications, standards or other material not created by
PICMG. Such referenced materials will typically have been created by organizations that operate
under IPR policies with terms that vary widely, and under process controls with varying degrees
of strictness and efficacy. PICMG has not made any enquiry into the nature or effectiveness of
any such policies, processes or controls, and therefore ANY USE OF REFERENCED
MATERIALS IS ENTIRELY AT THE RISK OF THE USER. Users should therefore make such
investigations regarding referenced materials, and the organizations that have created them, as
they deem appropriate.
PICMG®, CompactPCI®, AdvancedTCA®, AdvancedTCA® 300,ATCA®, ATCA® 300,
AdvancedMC®, CompactPCI® Express, COM Express®, MicroTCA®, SHB Express®, and the
PICMG, CompactPCI, AdvancedTCA, µTCA and ATCA logos are registered trademarks, and
xTCA™, IRTM™ and the IRTM logo are trademarks of the PCI Industrial Computer
Manufacturers Group. All other brand or product names may be trademarks or registered
trademarks of their respective holders.
PICMG
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COM Express
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Carrier Board Design Guide Rev. 2.0 / December 6, 2013
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Contents
1. Preface..................................................................................................................................8
1.1. About This Document........................................................................................................... 8
1.2. Intended Audience................................................................................................................ 8
1.3. No special word usage.........................................................................................................8
1.4. No statements of compliance..............................................................................................8
1.5. Correctness Disclaimer........................................................................................................8
1.6. Name and logo usage........................................................................................................... 9
1.7. Intellectual property............................................................................................................ 10
1.8. Acronyms, Abbreviations and Definitions Used...............................................................11
1.9. Signal Table Terminology...................................................................................................14
1.10. Schematic Conventions......................................................................................................15
2. COM Express Interfaces....................................................................................................16
2.1. COM Express Signals.........................................................................................................16
2.1.1. Connector Pin-out Comparison.......................................................................................20
2.2. PCIe General Introduction..................................................................................................30
2.2.1. COM Express A-B Connector and C-D Connector PCIe Groups....................................30
2.3. General Purpose PCIe Lanes.............................................................................................31
2.3.1. General Purpose PCIe Signal Definitions.......................................................................31
2.3.2. PCI Express Lane Configurations – Per COM Express Spec.........................................32
2.3.3. PCI Express Lane Configurations – Module and Chipset Dependencies.......................32
2.3.4. Device Up / Device Down and PCIe Rx / Tx Coupling Capacitors..................................33
2.3.5. Schematic Examples.......................................................................................................34
2.3.6. PCI Express Routing Considerations..............................................................................47
2.4. PEG (PCI Express Graphics)..............................................................................................48
2.4.1. Signal Definitions.............................................................................................................48
2.4.2. PEG Configuration...........................................................................................................49
2.4.3. Reference Schematics.....................................................................................................52
2.4.4. Routing Considerations...................................................................................................53
2.5. Digital Display Interfaces....................................................................................................55
2.5.1. DisplayPort / HDMI / DVI ................................................................................................55
2.5.2. SDVO...............................................................................................................................61
2.6. Mobile PCI Express Module (MXM)....................................................................................66
2.6.1. Signal Definitions.............................................................................................................66
2.6.2. Reference Schematics.....................................................................................................68
2.6.3. Routing Considerations...................................................................................................69
2.7. LAN....................................................................................................................................... 70
2.7.1. Signal Definitions.............................................................................................................70
2.7.2. Reference Schematics.....................................................................................................73
2.7.3. Routing Considerations...................................................................................................75
2.8. USB Ports............................................................................................................................ 76
2.8.1. Signal Definitions.............................................................................................................76
2.8.2. Reference Schematics.....................................................................................................77
2.8.3. Avoiding Back-driving Problems......................................................................................80
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2.8.4. Routing Considerations...................................................................................................80
2.9. USB 3.0................................................................................................................................ 81
2.9.1. Signal Definitions.............................................................................................................81
2.9.2. Reference Schematics.....................................................................................................84
2.9.3. Avoiding Back-driving Problems......................................................................................86
2.9.4. Routing Considerations...................................................................................................86
2.10. SATA..................................................................................................................................... 87
2.10.1. Signal Definitions.............................................................................................................87
2.10.2. Reference Schematic......................................................................................................89
2.10.3. Routing Considerations...................................................................................................90
2.11. LVDS..................................................................................................................................... 91
2.11.1. Signal Definitions.............................................................................................................91
2.11.2. Reference Schematics.....................................................................................................97
2.11.3. Routing Considerations...................................................................................................98
2.12. Embedded DisplayPort (eDP).............................................................................................99
2.12.1. Signal Definitions.............................................................................................................99
2.12.2. Reference Schematics..................................................................................................100
2.12.3. Routing Considerations.................................................................................................100
2.13. VGA.................................................................................................................................... 101
2.13.1. Signal Definitions...........................................................................................................101
2.13.2. VGA Connector..............................................................................................................101
2.13.3. VGA Reference Schematics..........................................................................................102
2.13.4. Routing Considerations.................................................................................................103
2.14. TV-Out................................................................................................................................ 104
2.15. Digital Audio Interfaces....................................................................................................105
2.15.1. Reference Schematics..................................................................................................107
2.16. LPC Bus – Low Pin Count Interface.................................................................................111
2.16.1. Signal Definition.............................................................................................................111
2.16.2. LPC Bus Reference Schematics....................................................................................111
2.16.3. Routing Considerations..................................................................................................116
2.17. SPI – Serial Peripheral Interface Bus...............................................................................118
2.17.1. Signal Definition.............................................................................................................118
2.17.2. SPI Reference Schematics............................................................................................119
2.17.3. Routing Considerations.................................................................................................120
2.18. General Purpose I2C Bus Interface.................................................................................121
2.18.1. Signal Definitions...........................................................................................................121
2.18.2. Reference Schematics..................................................................................................121
2.18.3. Connectivity Considerations..........................................................................................122
2.19. System Management Bus (SMBus).................................................................................123
2.19.1. Signal Definitions...........................................................................................................123
2.19.2. Routing Considerations.................................................................................................124
2.20. General Purpose Serial Interface.....................................................................................125
2.20.1. Signal Definitions...........................................................................................................125
2.20.2. Reference Schematics..................................................................................................126
2.20.3. Routing Considerations.................................................................................................126
2.21. CAN Interface....................................................................................................................127
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2.21.1. Signal Definitions...........................................................................................................127
2.21.2. Reference Schematics..................................................................................................128
2.21.3. Routing Considerations.................................................................................................128
2.22. Miscellaneous Signals......................................................................................................129
2.22.1. Module Type Detection..................................................................................................130
2.22.2. Speaker Output..............................................................................................................130
2.22.3. RTC Battery Implementation.........................................................................................131
2.22.4. Power Management Signals..........................................................................................133
2.22.5. Watchdog Timer.............................................................................................................135
2.22.6. General Purpose Input/Output (GPIO)..........................................................................136
2.22.7. SDIO Interface Multiplexed with GPIOs........................................................................138
2.22.8. Fan Connector...............................................................................................................140
2.22.9. Thermal Interface...........................................................................................................141
2.22.10. Protecting COM.0 Pins Reclaimed From the VCC_12V Pool.......................................142
2.23. PCI Bus..............................................................................................................................145
2.23.1. Signal Definitions...........................................................................................................145
2.23.2. Reference Schematics..................................................................................................146
2.23.3. Routing Considerations.................................................................................................149
2.24. IDE and CompactFlash (PATA).........................................................................................151
2.24.1. Signal Definitions...........................................................................................................151
2.24.2. IDE 40-Pin Header (3.5 Inch Drives).............................................................................152
2.24.3. IDE 44-Pin Header (2.5 Inch and Low Profile Optical Drives).......................................152
2.24.4. CompactFlash 50 Pin Header.......................................................................................152
2.24.5. IDE / CompactFlash Reference Schematics.................................................................152
2.24.6. Routing Considerations.................................................................................................153
3. Power and Reset..............................................................................................................154
3.1. General Power requirements...........................................................................................154
3.1.1. VCC_12V Rise Time Caution and Inrush Currents.......................................................154
3.2. ATX and AT Style Power Control......................................................................................155
3.2.1. ATX vs AT Supplies........................................................................................................155
3.2.2. Power States..................................................................................................................155
3.2.3. ATX and AT Power Sequencing Diagrams....................................................................156
3.2.4. Power Monitoring Circuit Discussion.............................................................................159
3.2.5. Power Button.................................................................................................................160
3.3. Design Considerations for Carrier Boards containing FPGAs/CPLDs.........................161
3.4. Reference Schematics......................................................................................................162
3.4.1. ATX Power Supply.........................................................................................................162
3.5. Routing Considerations....................................................................................................165
3.5.1. VCC_12V and GND.......................................................................................................165
3.5.2. Copper Trace Sizing and Current Capacity...................................................................165
3.5.3. VCC5_SBY Routing.......................................................................................................166
3.5.4. Power State and Reset Signal Routing.........................................................................166
3.5.5. Slot Card Supply Decoupling Recommendations.........................................................167
4. BIOS Considerations.......................................................................................................168
4.1. Legacy versus Legacy-Free.............................................................................................168
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