PCI Express Base Specification 2.1

PCI Express

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Contents

OBJECTIVE OF THE SPECIFICATION.................................................................................... 25

DOCUMENT ORGANIZATION ................................................................................................ 25

1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 39

1.3.1. Root Complex........................................................................................................ 39

1.3.2. Endpoints .............................................................................................................. 40

1.3.3. Switch.................................................................................................................... 43

1.3.4. Root Complex Event Collector.............................................................................. 44

1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 44

1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 44

1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 45

1.5.1. Transaction Layer................................................................................................. 46

1.5.2. Data Link Layer.................................................................................................... 46

2.1.2. Packet Format Overview ...................................................................................... 54

2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 56

2.2.1. Common Packet Header Fields ............................................................................ 56

2.2.2. TLPs with Data Payloads - Rules......................................................................... 59

2.2.3. TLP Digest Rules .................................................................................................. 63

2.2.4. Routing and Addressing Rules.............................................................................. 63

2.2.5. First/Last DW Byte Enables Rules........................................................................ 67

2.2.6. Transaction Descriptor......................................................................................... 70

2.2.7. Memory, I/O, and Configuration Request Rules................................................... 75

2.2.8. Message Request Rules......................................................................................... 81

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2.3.2. Completion Handling Rules................................................................................ 117

2.4. TRANSACTION ORDERING............................................................................................ 119

2.4.1. Transaction Ordering Rules ............................................................................... 119

2.4.2. Update Ordering and Granularity Observed by a Read Transaction................ 123

2.4.3. Update Ordering and Granularity Provided by a Write Transaction................ 124

2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 125

2.5.1. Virtual Channel Identification (VC ID).............................................................. 127

2.5.2. TC to VC Mapping.............................................................................................. 128

2.5.3. VC and TC Rules................................................................................................. 129

2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 130

2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 149

2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 150

3. DATA LINK LAYER SPECIFICATION.......................................................................... 151

3.1. DATA LINK LAYER OVERVIEW .................................................................................... 151

3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 153

3.2.1. Data Link Control and Management State Machine Rules ................................ 154

3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 156

3.3.1. Flow Control Initialization State Machine Rules ............................................... 156

3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 160

3.4.1. Data Link Layer Packet Rules ............................................................................ 160

4.2. LOGICAL SUB-BLOCK................................................................................................... 187

4.2.1. Symbol Encoding ................................................................................................ 188

4.2.2. Framing and Application of Symbols to Lanes................................................... 191

4.2.3. Data Scrambling................................................................................................. 194

4.2.4. Link Initialization and Training.......................................................................... 196

4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 208

4.2.6. Link Training and Status State Rules.................................................................. 212

4.2.7. Clock Tolerance Compensation.......................................................................... 258

4.2.8. Compliance Pattern ............................................................................................ 260

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4.3.3. Transmitter Specification.................................................................................... 265

4.3.5. Transmitter and Receiver DC Specifications...................................................... 293

4.3.6. Channel Specifications........................................................................................ 298

4.3.7. Reference Clock Specifications........................................................................... 305

6.2.4. Error Logging..................................................................................................... 371

6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 376

6.2.6. Error Message Controls ..................................................................................... 378

6.2.7. Error Listing and Rules ...................................................................................... 379

6.2.8. Virtual PCI Bridge Error Handling.................................................................... 384

6.2.9. Internal Errors.................................................................................................... 386

6.3.1. Introduction and Scope....................................................................................... 386