################################################################################
# Vivado (TM) v2021.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "xcelium", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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基于vivado DDS ip核的DDS信号发生器(可调频调相)
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基于vivado DDS ip核的DDS信号发生器(可调频调相) (202个子文件)
__synthesis_is_complete__ 0B
xsim.ini.bak 28KB
elaborate.bat 1KB
simulate.bat 1KB
compile.bat 1KB
runme.bat 229B
design_1.bd 12KB
design_1.bda 2KB
design_1.bda 2KB
design_1.bda 2KB
design_1.bda 2KB
design_1.bda 2KB
design_1.bda 2KB
design_1.bda 2KB
design_1.bda 2KB
design_1.bda 2KB
design_1.bda 2KB
design_1.bxml 3KB
xsim_1.c 21KB
ssm.db 591B
xsim.dbg 15KB
design_1_ila_0_0.dcp 536KB
design_1_dds_compiler_0_0.dcp 108KB
design_1_dds_compiler_0_0.dcp 101KB
design_1_dds_compiler_0_0.dcp 96KB
design_1_dds_compiler_0_0.dcp 96KB
design_1_dds_compiler_0_0.dcp 95KB
compile.do 3KB
compile.do 2KB
compile.do 2KB
simulate.do 574B
simulate.do 561B
simulate.do 561B
compile.do 400B
elaborate.do 390B
simulate.do 242B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 229KB
run.f 2KB
design_1.hwdef 5KB
design_1.hwh 28KB
modelsim.ini 135KB
xsim.ini 28KB
xsim.ini 28KB
xsimSettings.ini 1KB
vivado.jou 960B
ISEWrap.js 8KB
rundef.js 1KB
runme.log 31KB
elaborate.log 5KB
xvlog.log 597B
compile.log 597B
xsimkernel.log 318B
simulate.log 134B
xvhdl.log 0B
xsimcrash.log 0B
ddsip_test.lpr 290B
xsim.mem 422KB
xsim_0.win64.obj 185KB
xsim_1.win64.obj 13KB
elab.opt 409B
vivado.pb 48KB
xelab.pb 9KB
xvlog.pb 1KB
design_1_dds_compiler_0_0_utilization_synth.pb 224B
xvhdl.pb 16B
dds_tb_vlog.prj 376B
dds_tb_vhdl.prj 216B
vhdl.prj 123B
vlog.prj 113B
design_1.protoinst 1KB
design_1.protoinst 1KB
design_1.protoinst 1KB
design_1.protoinst 1KB
xsim.reloc 16KB
xsim.rlx 944B
xil_defaultlib.rlx 827B
design_1_dds_compiler_0_0_utilization_synth.rpt 8KB
.vivado.begin.rst 218B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
xsim.rtti 468B
design_1.sdb 10KB
glbl.sdb 4KB
design_1_wrapper.sdb 2KB
dds_tb.sdb 2KB
design_1_ila_0_0.sdb 641B
design_1.sh 9KB
design_1.sh 6KB
design_1.sh 6KB
design_1.sh 5KB
design_1.sh 5KB
design_1.sh 5KB
design_1.sh 5KB
ISEWrap.sh 2KB
runme.sh 1KB
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