FIR Compiler v7.2 www.xilinx.com 4
PG149 November 18, 2015 Product Specification
Introduction
The Xilinx® LogiCORE™ IP FIR Compiler core
provides a common interface to generate
highly parameterizable, area-efficient
high-performance FIR filters.
Features
• AXI4-Stream-compliant interfaces
• High-performance finite impulse response
(FIR), polyphase decimator, polyphase
interpolator, half-band, half-band
decimator and half-band interpolator,
Hilbert transform and interpolated filter
implementations
• Support for up to 256 sets of coefficients,
with 2 to 2048 coefficients per set
• Input data up to 49-bit precision
• Filter coefficients up to 49-bit precision
• Support for up to 1024 interleaved data
channels
• Support for advanced interleaved data
channel sequences
• Support for multiple parallel data channels
with shared control logic
• Interpolation and decimation factors of up
to 64 generally and up to 1024 for single
channel filters
• Support for sample frequency greater than
clock frequency
• Online coefficient reload capability
• User-selectable output rounding
• Efficient multi-column structures for all
filter implementations and optimizations
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
UltraScale+™ Families
UltraScale™ Architecture
Zynq-7000 All Programmable SoC
7 Series
Supported User
Interfaces
AXI4-Stream
Resources Performance and Resource Utilization web page
Provided with Core
Design Files Encrypted RTL
Example Design Not Provided
Tes t Be nch VHDL
Constraints File Not Provided
Simulation
Model
Encrypted VHDL
Supported
S/W Driver
N/A
Tested Design Flows
(2)
Design Entry
Vivado® Design Suite
System Generator for DSP
Simulation
For supported simulators, see the
X
ilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Provided by Xilinx at the at the Xilinx Support web page
Notes:
1. For a complete listing of supported devices, see the Vivado IP
catalog.
2. For the supported versions of the tools, see the
X
ilinx Design Tools: Release Notes Guide.
AshleyK2023-07-26文件结构清晰，每个步骤都有明确的解释和演示代码，使得读者能够轻松跟随并实践。
林祈墨2023-07-26文中给出了一些实用的例子和问题解答，能够帮助读者更好地理解和应用fir IP核。
Xhinking2023-07-26这篇文件虽然简短，但提供了足够的信息和资源，是一个值得推荐的参考文献。
基鑫阁2023-07-26这篇文件对于初学者而言非常友好，清晰地介绍了vivado fir IP核的使用方法。
ask_ai_app2023-07-26文件中详细说明了fir滤波器的原理和实现步骤，对于需要使用该功能的人来说，是一个不错的指导。
