################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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Xilinx 乘法器IP的使用 行为仿真 完整工程 vivado 2018.3 和 modelsim SE 10.7
共152个文件
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do:17个
vhd:11个
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2022-03-24
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Xilinx 乘法器IP的使用 vivado 2018.3 和 modelsim SE 10.7 完成 教程来自 https://blog.csdn.net/MaoChuangAn/article/details/82999909
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Xilinx 乘法器IP的使用 行为仿真 完整工程
vivado 2018.3 和 modelsim SE 10.7 (152个子文件)
__synthesis_is_complete__ 0B
_info 3KB
_info 145B
_info 145B
_info 145B
_vmake 29B
simulate.bat 800B
compile.bat 794B
runme.bat 229B
point_mul.dcp 389KB
point_mul.dcp 389KB
point_mul.dcp 389KB
compile.do 1KB
compile.do 1KB
compile.do 940B
compile.do 918B
tb_mul_compile.do 779B
tb_mul_simulate.do 682B
tb_mul_wave.do 339B
simulate.do 338B
simulate.do 333B
simulate.do 333B
elaborate.do 210B
simulate.do 195B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
simulate.do 11B
run.f 558B
run.f 538B
modelsim.ini 119KB
xsim.ini 22KB
vivado.jou 758B
ISEWrap.js 7KB
rundef.js 1KB
runme.log 23KB
simulate.log 2KB
compile.log 2KB
my_multiplier.lpr 290B
elab.opt 222B
vivado.pb 35KB
point_mul_utilization_synth.pb 289B
仿真波形图,演示十乘以十.png 343KB
vhdl.prj 111B
_lib4_0.qdb 80KB
_lib.qdb 64KB
_lib5_0.qdb 64KB
_lib.qdb 48KB
_lib1_0.qdb 32KB
_lib6_0.qdb 32KB
_lib2_0.qdb 32KB
_lib1_0.qdb 32KB
_lib3_0.qdb 32KB
_lib4_0.qpg 12.04MB
_lib5_0.qpg 7.82MB
_lib2_0.qpg 3.02MB
_lib3_0.qpg 1.32MB
_lib1_0.qpg 920KB
_lib6_0.qpg 40KB
_lib1_0.qpg 0B
_lib2_0.qtl 205KB
_lib5_0.qtl 183KB
_lib3_0.qtl 177KB
_lib1_0.qtl 110KB
_lib4_0.qtl 70KB
_lib1_0.qtl 14KB
_lib6_0.qtl 9KB
point_mul_utilization_synth.rpt 7KB
.vivado.begin.rst 181B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
point_mul.sh 7KB
point_mul.sh 6KB
point_mul.sh 6KB
point_mul.sh 6KB
point_mul.sh 5KB
point_mul.sh 5KB
point_mul.sh 5KB
point_mul.sh 5KB
ISEWrap.sh 2KB
runme.sh 1KB
point_mul.tcl 9KB
cmd.tcl 464B
mult_gen_v12_0_changelog.txt 7KB
README.txt 3KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
file_info.txt 513B
file_info.txt 513B
file_info.txt 513B
file_info.txt 513B
file_info.txt 513B
file_info.txt 513B
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