################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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Vivado DDS IP核仿真
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Vivado DDS IP核仿真 (179个子文件)
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 2KB
simulate.bat 1KB
compile.bat 964B
runme.bat 229B
xsim_1.c 16KB
xsim.dbg 12KB
dds_compiler_0.dcp 94KB
dds_compiler_0.dcp 94KB
dds_compiler_0.dcp 94KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
simulate.do 486B
simulate.do 479B
simulate.do 479B
elaborate.do 351B
compile.do 265B
simulate.do 205B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
simulate.do 11B
xsimk.exe 442KB
run.f 1KB
run.f 1KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 64B
modelsim.ini 126KB
xsim.ini 26KB
xsim.ini 25KB
xsimSettings.ini 1KB
webtalk.jou 954B
webtalk_7184.backup.jou 953B
vivado.jou 832B
ISEWrap.js 8KB
rundef.js 1KB
runme.log 32KB
webtalk.log 1023B
webtalk_7184.backup.log 1022B
elaborate.log 778B
xsimkernel.log 316B
simulate.log 50B
xvlog.log 0B
compile.log 0B
xsimcrash.log 0B
xvhdl.log 0B
ASK.lpr 290B
xsim.mem 423KB
xsim_0.win64.obj 393KB
xsim_1.win64.obj 11KB
elab.opt 363B
vivado.pb 51KB
xelab.pb 1KB
dds_compiler_0_utilization_synth.pb 289B
xvhdl.pb 16B
xvlog.pb 16B
tb_vlog.prj 319B
tb_vhdl.prj 176B
vhdl.prj 111B
xsim.reloc 14KB
xsim.rlx 987B
xil_defaultlib.rlx 856B
dds_compiler_0_utilization_synth.rpt 7KB
.vivado.begin.rst 209B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
xsim.rtti 468B
glbl.sdb 4KB
dds_top.sdb 2KB
dds_ctl.sdb 2KB
tb.sdb 1KB
dds_compiler_0.sh 8KB
dds_compiler_0.sh 6KB
dds_compiler_0.sh 6KB
dds_compiler_0.sh 6KB
dds_compiler_0.sh 5KB
dds_compiler_0.sh 5KB
dds_compiler_0.sh 5KB
dds_compiler_0.sh 5KB
ISEWrap.sh 2KB
runme.sh 1KB
xsim.svtype 66B
dds_compiler_0.tcl 10KB
xsim_webtalk.tcl 4KB
cmd.tcl 464B
tb.tcl 460B
dds_compiler_v6_0_changelog.txt 9KB
README.txt 3KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
file_info.txt 1KB
共 179 条
- 1
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