################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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温馨提示
1)通过按键选择输出波形,包括正弦波、矩形波、锯齿波、三角波; 2)输出频率可调,从 10Hz~1MHz,频率步进为 1Hz; 3)输出幅度可调,幅度量化位数为 16bit,峰值能够从 0~65535 之间任 意设置; 4)矩形波占空比可调,占空比从 0~99%,步进为 1%。 fpga软件 vivado 2018.3; 配有rom所需的coe文件 配有matlab进行生成coe采样文件的m文件 矩形波占空比有单独的生成文件,没有采用查找表的rom形式。 点击仿真既可开始产生结果图。 点击文件即可运行,若vivado版本小于2018.3可能ip核会更新错误
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dds 信号发生器:可产生正弦波、锯齿波、三角波、矩形波;频率、幅度、占空比可调; (1244个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
_info 4KB
_info 750B
_info 85B
_info 85B
_vmake 26B
_vmake 26B
xsim.ini.bak 23KB
elaborate.bat 938B
compile.bat 830B
compile.bat 823B
simulate.bat 792B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
xsim_2.c 426KB
xsim_1.c 63KB
xsim_1.c 24KB
xsim_1.c 7KB
hz_1000000x32.coe 10.37MB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
tri_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
saw_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
sin_wave_4096x16.coe 31KB
squ_wave_4096x16.coe 24KB
squ_wave_4096x16.coe 24KB
squ_wave_4096x16.coe 24KB
squ_wave_4096x16.coe 24KB
squ_wave_4096x16.coe 24KB
squ_wave_4096x16.coe 24KB
_primary.dat 8KB
_primary.dat 6KB
_primary.dat 5KB
_primary.dat 4KB
_primary.dat 3KB
_primary.dat 3KB
_primary.dat 2KB
_primary.dat 2KB
_primary.dat 2KB
_primary.dat 2KB
_primary.dat 2KB
_primary.dat 1KB
xsim.dbg 82KB
xsim.dbg 16KB
xsim.dbg 10KB
_primary.dbs 26KB
_primary.dbs 22KB
_primary.dbs 14KB
_primary.dbs 12KB
_primary.dbs 9KB
_primary.dbs 7KB
_primary.dbs 5KB
_primary.dbs 3KB
_primary.dbs 874B
_primary.dbs 874B
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