################################################################################
# Vivado (TM) v2017.4 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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具于xilinx FPGA的可动态配置DDS频率控制字的DDS IP核使用例程(examples ) 本examples 是月隐编写的针对DDS的使用demo,实现通过vio控制频率控制字来调整DDS的输出频率,为大家演示一个可动态配置DDS频率的例程。 例程的平台: 1) 硬件平台:XC7Z020CLG484-2 2) FPGA开发平台:vivado2017.4 3) 可仿真
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具于xilinx FPGA的可动态配置DDS频率控制字的DDS IP examples (使用例程) (505个子文件)
runme.bat 229B
runme.bat 229B
runme.bat 229B
design_1.bd 1KB
dds_demo.bit 809KB
dds_demo.bit 809KB
design_1.bxml 604B
dds_demo_routed.dcp 1.95MB
dds_demo_placed.dcp 1.72MB
dds_demo_opt.dcp 1.37MB
ila_0.dcp 644KB
ila_0.dcp 641KB
ila_0.dcp 641KB
ila_0.dcp 640KB
dbg_hub_CV.dcp 333KB
vio_0.dcp 121KB
vio_0.dcp 121KB
dds_compiler_0.dcp 78KB
dds_compiler_0.dcp 78KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
dds_demo.dcp 7KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 881B
compile.do 857B
compile.do 816B
compile.do 806B
compile.do 803B
compile.do 779B
compile.do 738B
compile.do 728B
simulate.do 536B
simulate.do 536B
simulate.do 536B
elaborate.do 408B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 303B
simulate.do 303B
simulate.do 294B
simulate.do 294B
simulate.do 294B
simulate.do 294B
simulate.do 205B
simulate.do 195B
simulate.do 187B
simulate.do 187B
elaborate.do 183B
elaborate.do 175B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
simulate.do 11B
run.f 1KB
run.f 520B
run.f 440B
run.f 440B
usage_statistics_webtalk.html 188KB
xsim.ini 19KB
xsim.ini 19KB
xsim.ini 19KB
xsim.ini 19KB
vivado.jou 763B
vivado.jou 762B
vivado.jou 757B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 120KB
runme.log 120KB
runme.log 119KB
runme.log 37KB
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资源评论
- purpleisland2024-04-30资源内容总结地很全面,值得借鉴,对我来说很有用,解决了我的燃眉之急。
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