################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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64-Vivado DDS IP核混频设计.7z
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64-Vivado DDS IP核混频设计.7z (271个子文件)
xsim.ini.bak 26KB
elaborate.bat 2KB
compile.bat 980B
simulate.bat 900B
xsim_1.c 20KB
xsim.dbg 10KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 1KB
compile.do 1KB
compile.do 947B
compile.do 925B
simulate.do 482B
simulate.do 482B
simulate.do 482B
simulate.do 482B
simulate.do 481B
simulate.do 481B
elaborate.do 353B
elaborate.do 353B
simulate.do 345B
simulate.do 343B
simulate.do 343B
elaborate.do 217B
simulate.do 207B
simulate.do 207B
simulate.do 201B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
simulate.do 11B
simulate.do 11B
simulate.do 11B
xsimk.exe 1.01MB
run.f 1KB
run.f 1KB
run.f 1KB
run.f 1KB
run.f 562B
run.f 542B
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 64B
xsim.ini 26KB
xsim.ini 25KB
xsim.ini 25KB
xsim.ini 25KB
xsimSettings.ini 1KB
vivado.jou 7KB
webtalk_17384.backup.jou 997B
webtalk.jou 997B
vivado.log 20KB
elaborate.log 5KB
webtalk.log 1KB
webtalk_17384.backup.log 1KB
compile.log 1KB
xvhdl.log 744B
xvlog.log 424B
xsimkernel.log 323B
xsimcrash.log 144B
simulate.log 50B
design_top.lpr 290B
xsim.mem 441KB
xsim_0.win64.obj 1003KB
xsim_1.win64.obj 14KB
elab.opt 365B
elab.opt 365B
elab.opt 229B
xelab.pb 9KB
xvhdl.pb 1KB
xvlog.pb 724B
64-Vivado DDS IP核混频设计.pdf 104KB
top_tb_vhdl.prj 351B
top_tb_vlog.prj 234B
vhdl.prj 120B
vhdl.prj 120B
vhdl.prj 114B
xsim.reloc 22KB
xsim.rlx 1013B
xil_defaultlib.rlx 798B
xsim.rtti 468B
glbl.sdb 4KB
top_tb.sdb 2KB
dds_compiler_4M.sh 8KB
dds_compiler_5M.sh 8KB
Multiplier_X.sh 7KB
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