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UltraFast Design

Methodology Guide for

FPGAs and SoCs

UG949 (v2023.1) June 7, 2023

See all versions

of this document

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that end, we’re removing non-inclusive language from our products

and related collateral. We’ve launched an internal initiative to remove

language that could exclude people or reinforce historical biases,

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examples of non-inclusive language in our older products as we work

to make these changes and align with evolving industry standards.

Follow this link for more information.

Table of Contents

Chapter 1: Introduction............................................................................................. 4

About the UltraFast Design Methodology................................................................................4

Understanding UltraFast Design Methodology Concepts..................................................... 7

Using the Vivado Design Suite.................................................................................................11

Accessing Additional Documentation and Training..............................................................12

Chapter 2: Board and Device Planning............................................................. 13

PCB Layout Recommendations............................................................................................... 13

Device Power Aspects and System Dependencies................................................................19

Clock Resource Planning and Assignment.............................................................................22

I/O Planning Design Flows.......................................................................................................22

Designing with SSI Devices...................................................................................................... 28

Designing with HBM Devices...................................................................................................35

Configuration.............................................................................................................................39

Chapter 3: Design Creation with RTL.................................................................41

Defining a Good RTL Design Hierarchy.................................................................................. 42

Working with Intellectual Property (IP)..................................................................................46

RTL Coding Guidelines..............................................................................................................49

Clocking Guidelines...................................................................................................................88

Clock Domain Crossing...........................................................................................................140

Chapter 4: Design Constraints.............................................................................145

Organizing the Design Constraints for Compilation.......................................................... 145

Defining Timing Constraints..................................................................................................151

Defining Power and Thermal Constraints............................................................................185

Defining Physical Constraints................................................................................................186

Chapter 5: Design Implementation..................................................................187

Running Synthesis...................................................................................................................187

Moving Past Synthesis............................................................................................................195

Implementing the Design...................................................................................................... 200

UG949 (v2023.1) June 7, 2023

UltraFast Design Methodology Guide for FPGAs and SoCs 2

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Chapter 1

Introduction

About the UltraFast Design Methodology

The AMD UltraFast™ design methodology is a set of best pracces intended to help streamline

the design process for today's devices. The size and complexity of these designs require specic

steps and design tasks to ensure success at each stage of the design. Following these steps and

adhering to the best pracces will help you achieve your desired design goals as quickly and

eciently as possible.

• This guide, which describes the various design tasks, analysis and reporng features, and best

pracces for design creaon and closure.

• UltraFast Design Methodology Quick Reference Guide (UG1231), which highlights key design

methodology steps in an easy-to-use, double-sided card format.

• UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292), which covers

recommendaons for closing ming, including running inial design checks, baselining the

design, and resolving ming violaons.

• UltraFast Design Methodology Checklist (XTP301), which is available in the AMD

Documentaon Navigator and as a standalone spreadsheet. You can use this checklist to

idenfy common mistakes and decision points throughout the design process.

• UltraFast Design Methodology System-Level Design Flow diagram represenng the enre

AMD Vivado™ Design Suite design ow, which is available in the AMD Documentaon

Navigator. You can click a design step in the diagram to open related documentaon,

collateral, and FAQs to help get you started.

RECOMMENDED: In addion to these resources, AMD recommends the UltraFast Embedded Design

Methodology Guide (UG1046) when working with embedded designs and the HLS Programmers Guide

in the Vis HLS User Guide (UG1399) when developing complex systems using Vivado IP integrator

with C-based IP.

AMD provides the following resources to help you take advantage of the UltraFast design

methodology:

TIP:

AMD also provides methodology-related design rule checks (DRCs) for each design stage, which are

available using the

report_methodology

  Tcl command in the Vivado Design Suite.

Chapter 1: Introduction

UG949 (v2023.1) June 7, 2023

UltraFast Design Methodology Guide for FPGAs and SoCs 4

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Using This Guide

This guide provides a set of best pracces that maximize producvity for both system integraon

and design implementaon. It includes high-level informaon, design guidelines, and design

decision trade-os for the following topics:

• Chapter 2: Board and Device Planning: Covers decisions and design tasks that AMD

recommends accomplishing prior to design creaon. These include I/O and clock planning,

PCB layout consideraons, device capacity and throughput assessment, alternate device

denion, power esmaon, and debugging.

• Chapter 3: Design Creaon with RTL: Covers the best pracces for RTL denion and IP

conguraon and management.

• Chapter 4: Design Constraints: Provides recommendaons for creang proper ming, power,

and physical constraints as well as specifying addional constraints, aributes, and other

elements used during synthesis and implementaon.

• Chapter 5: Design Implementaon: Covers the opons available and best pracces for

synthesizing and implemenng the design.

• Chapter 6: Design Closure: Covers the various design analysis and implementaon techniques

used to close ming on the design or to reduce power consumpon. It also includes

consideraons for adding debug logic to the design for hardware vericaon purposes.

This guide includes references to other documents such as the Vivado Design Suite User Guides,

Vivado Design Suite Tutorials, and Quick-Take Video Tutorials. This guide is not a replacement for

those documents. AMD sll recommends referring to those documents for detailed informaon,

including descripons of tool use and design methodology.

This informaon is designed for use with the Vivado Design Suite, but you can use most of the

conceptual informaon with the ISE

Design Suite as well.

Related Information

Addional Resources and Legal Noces

Using the UltraFast Design Methodology Checklist

To take full advantage of the UltraFast design methodology, use this guide with the UltraFast

Design Methodology Checklist (XTP301). The checklist is available from the AMD Documentaon

Navigator or as a standalone spreadsheet.

The quesons in the UltraFast Design Methodology Checklist highlight typical areas in which

design decisions are likely to have downstream impact and draw aenon to issues that are

oen overlooked or ignored. Each tab in the checklist:

• Targets a specic role within a typical design team.

Chapter 1: Introduction

UG949 (v2023.1) June 7, 2023

UltraFast Design Methodology Guide for FPGAs and SoCs 5

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