Using Constraints Tutorial
IMPORTANT! This tutorial requires using AMD Kintex™ 7 family of devices. You will need to update your
AMD Vivado™ tools installaon if you do not have this device family installed. Refer to the Vivado Design
Suite User Guide: Release Notes, Installaon, and Licensing (UG973) for more informaon on Adding
Design Tools or Devices.
This tutorial comprises of two labs that demonstrate the aspects of constraining a design in the
AMD Vivado™ Design Suite. The constraints format supported by the AMD Vivado™ Design
Suite is called Xilinx Design Constraints (XDC), which is a combinaon of the industry standard
Synopsys
®
Design Constraints and proprietary Xilinx constraints. For more informaon on Timing
Closure, see the UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292).
VIDEO: You can also learn more about dening constraints in the Vivado Design Suite by viewing the
quick take video at Vivado Design Constraints Overview.
TRAINING: AMD provides training courses that can help you learn more about the concepts presented in
this document. Use these links to explore related courses:
• Essenals of FPGA Design
• Vivado Design Suite Stac Timing Analysis and Xilinx Design Constraints
XDCs are not just simple strings; they are Tcl commands that the Vivado Tcl interpreter
sequenally reads and parses. You can enter design constraints in several ways at dierent points
in the design ow. You can store XDCs in one or more les that can be added to a constraint set
in Vivado Project mode, or read the same les directly into memory using the read_xdc
command in Non-Project mode. For more informaon on Project and Non-Project modes, refer
to the Vivado Design Suite User Guide: Design Flows Overview (UG892). With a design open in
Vivado tools, you can also type constraints as commands directly in the Tcl Console when
working in the Vivado IDE or at the Tcl command prompt when working outside of the IDE. This
is parcularly powerful for dening, validang, and debugging new constraints interacvely in
the design.
The Vivado Design Suite synthesis and implementaon tools are ming driven. Having accurate
and correct ming constraints is vital for meeng design goals and ensuring correct operaon.
Because the Vivado tools are ming driven, it is important to fully constrain a design, but not
over-constrain, or under-constrain it. Over-constraining a design can lead to long compile mes
and sub-opmal results because the tool can struggle with unrealisc design objecves. Under-
constraining a design can cause the Vivado tools to perform unnecessary opmizaons, such as
examining paths with mulcycle delays or false paths, and prevent focus on the real crical paths.
This tutorial discusses dierent methods for dening and applying design constraints.
Using Constraints Tutorial
UG945 (v2023.1) May 30, 2023
Using Constraints 3
