7 Series FPGAs
Packaging and Pinout
Product Specification
UG475 (v1.11) March 18, 2014
7 Series FPGAs Packaging www.xilinx.com UG475 (v1.11) March 18, 2014
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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/01/2011 1.0 Initial Xilinx release.
04/06/2011 1.1 Removed the SBG324 package from the entire document. Added three Kintex®-7
devices: XC7K355T, XC7K420T, and XC7K480T.
Updated disclaimer and copyright on page 2. Updated package size of FF1156 in
Table 1-1. Updated DXP_0, DXN_0 in Table 1-11.
The Table 2-2 single ASCII device files have been updated for both the XC7K70T and
XC7K160T. All ASCII TXT files and the overall ZIP file have been updated on the web.
Updated the XC7K70TFBG676 figures: Figure 3-49, Figure 3-50, Figure 3-51, and
Figure 3-52.
Added information to Chapter 4, Mechanical Drawings, Chapter 5, Thermal
Specifications, and Chapter 6, Package Marking.
UG475 (v1.11) March 18, 2014 www.xilinx.com 7 Series FPGAs Packaging
06/14/2011 1.2 Added Virtex®-7 device information including updating Table 1-1, adding Table 1-3,
Table 1-9, Table 2-3, and Table 3-3. In Table 1-11, updated Note 3, the Configuration Pins
section, and the Analog to Digital Converter (XADC) Pins section.
Updated Figure 3-47, Figure 3-48, Figure 3-51, Figure 3-52, Figure 3-55, Figure 3-56,
Figure 3-59, Figure 3-60, Figure 3-63, Figure 3-64, Figure 3-67, and Figure 3-68. Added
Figure 3-68 through Figure 3-132.
Added Figure 4-28 the mechanical drawing for the Kintex-7 devices FFG1156 package.
Also added some Virtex-7 device mechanical drawings in Figure 4-28 through
Figure 4-34.
Added thermal resistance data to Table 5-1.
10/03/2011 1.3 Added Artix®-7 device information including updating Table 1-1, adding Table 1-3,
Table 1-7, Table 2-1, and Table 3-1.
Clarified the interposer in Figure-12 and Figure 1-14. Revised horizontal center for the
XC7VX415T in Figure 1-16. Updated the DXP_0, DXN_0 description and notes in
Table 1-11. Added devices to the Die Level Bank Numbering Overview section. Clarified
the I/O banks summary section.
Added Artix-7 device diagrams in the CSG324 package. Added XC7V585T device
diagrams Figure 3-81 through Figure 3-88.
Moved AD4P/N, AD12P/N, and AD5P/N pins from [IO_L2P_T0_35:IO_L4N_T0_35] to
[IO_L1P_T0_35:IO_L3N_T0_35] in Figure 3-89, Figure 3-93,
Figure 3-113, Figure 3-117,
Figure 3-121, Figure 3-125, and Figure 3-129.
Fixed the labeling for EMCCLK in Figure 3-73, Figure 3-81, Figure 3-89, Figure 3-93,
Figure 3-113, Figure 3-117, Figure 3-121, Figure 3-125, and Figure 3-129.
Updated the mechanical drawings for Figure 4-32 and Figure 4-34.
Updated thermal resistance data in Table 5-1.
Updated Chapter 6, Package Marking.
10/17/2011 1.4 Revised the FBG484 Package section describing XC7K160T Banks.
Added the mechanical drawings: Figure 4-32 and Figure 4-35. Updated Figure 4-34 to
include the FF(G)1928 package.
Added thermal resistance data to Table 5-1.
02/03/2012 1.5 Updated Table 1-3 and Table 1-5 and added Table 1-6. Updated Table 1-7 and Table 1-8
and added Table 1-9. Revised Note 2 in Table 1-11. Removed Figures 1-1 and 1-2 along
with references to the XC7A8, XC7A15, XC7A30T, and XC7A50T. Added Figure 1-5 and
Figure 1-3. Clarified Figure 1-9 though Figure 1-12, Figure 1-14, Figure 1-18, and
Figure 1-21.
Updated Table 2-3 and added Table 2-4.
Added devices to Table 3-1 and revised Table 3-2 (XC7K420T and XC7K480T). Updated
Table 3-3 and added Table 3-4 and Table 3-5.
Revised specifications in:
• Figure 4-15: FB/FBG484 Flip-Chip Lidless BGA (Kintex-7 FPGAs) (1.0 mm Pitch)
• Figure 4-18: FB/FBG676 Flip-Chip Lidless BGA (Kintex-7 FPGAs) (1.0 mm Pitch).
• Figure 4-23: FB/FBG900 Flip-Chip Lidless BGA (Kintex-7 FPGAs) (1.0 mm Pitch)
and combined with Figure 4-6.
• Figure 4-31: FF/FFG1157 and FF/FFG1158 Flip-Chip BGA (Virtex-7 FPGAs)
(1.0 mm Pitch).
Added thermal resistance data to Table 5-1 and added Soldering Guidelines section.
Added Appendix B.
Date Version Revision
7 Series FPGAs Packaging www.xilinx.com UG475 (v1.11) March 18, 2014
05/24/2012 1.6 Removed the FFG1933 and FLG1933 packages throughout. Added the FLG1926 package
where appropriate.
Updated the Introduction in Chapter 1. Updated XC7K420T in Table 1-9. Added Note 7
to Table 1-11. Updated the description and figure in the XC7K420T Banks and
XC7VX550T Banks sections.
Updated Figure 3-34, Figure 3-38, Figure 3-42, and Figure 3-34. Added Figure 3-157
through Figure 3-160.
Added Figure 4-7: FB/FBG676 Flip-Chip Lidless BGA Package Specifications for Artix-7
FPGAs. Revised specifications and added capacitor location figures for:
• Figure 4-18: FB/FBG676 Flip-Chip Lidless BGA Package Specifications for
Kintex-7 FPGAs
• Figure 4-21: XC7K325T FB/FBG676 Die Dimensions with Capacitor
Locations
• Figure 4-22: XC7K410T FB/FBG676 Die Dimensions with Capacitor
Locations
• Figure 4-23: FB/FBG900 Flip-Chip Lidless BGA Package Specifications for
Kintex-7 FPGAs
• Figure 4-24: XC7K325T FB/FBG900 Die Dimensions with Capacitor
Locations
• Figure 4-25: XC7K410T FB/FBG900 Die Dimensions with Capacitor
Locations
• Figure 4-28: FF/FFG1156 Flip-Chip BGA Package Specification for Kintex-7
FPGAs
• Figure 4-31: FF/FFG1157 and FF/FFG1158 Flip-Chip BGA Package Specification
for Virtex®-7 FPGAs
Added Thermal Management Strategy, Some Thermal Management Options, and
updated Soldering Guidelines in Chapter 5.
Updated Table A-1.
07/20/2012 1.7 In Table 1-11, updated the Other Pins section.
Added the XC7VH290T, XC7VH580T, and XC7VH870T and associated HCG packages to
all appropriate chapters, tables, and figures. Added the SBG484 package for the
XC7A200T devices to all appropriate chapters, tables, and figures.
Updated the XC7VX1140T-FLG1926 headings in Table 2-4, Figure 3-157 through
Figure 3-160, and
Figure 4-35.
Updated GTP Quad numbers in Figure 1-4, Figure 3-22, and Figure 3-26. Also added
numbers to Figure 3-25 and Figure 3-28. Updated the XC7V585T-FFG1761 figures:
Figure 3-85 and Figure 3-88.
Added new mechanical drawings for the Artix-7 FPGAs in Chapter 4 along with
Figure 4-20, Figure 4-35, and Figure 4-36, and updated Figure 4-27.
In Table 5-1, updated data throughout and added XC7VX1140T (FL1926) and
XC7VH580T data.
Added Figure 6-3: Artix-7 Device Package Marking.
10/15/2012 1.8 Removed the following devices: XC7A350T, XC7V1500T, XC7VH290T.
Added Figure 4-19 and updated drawing in Figure 4-20. Added Note 5 to Figure 4-31.
Updated A2 dimension in Figure 4-34. Updated aaa dimension in Figure 4-33 and
Figure 4-35.
Updated the JEDEC Moisture Sensitivity Level (MSL) for the Flip-Chip packages on
page 267.
Date Version Revision
UG475 (v1.11) March 18, 2014 www.xilinx.com 7 Series FPGAs Packaging
02/14/2013 1.9 Clarified pins in Figure 3-37.
Updated Figure 4-11 and Figure 4-15 and added Figure 4-16 and Figure 4-17. Revised
Figure 4-27 and Figure 4-31.
In Table 5-1, updated data for Artix®-7 FPGAs, XC7K160T FF/FFG676, Virtex®-7 T
FPGAs and XC7VX1140T.
Updated Appendix B.
11/15/2013 1.10 Updated disclaimer on page 2.
Added the XQ devices and RB/RF/RS package information throughout document.
Added Note 1 to Table 1-2 and Note 6 to Table 1-11. Revised the super logic region
numbers in Figure 1-20.
Removed the Virtex-7 HT devices (HCG packages). Before removal, revised the super
logic region numbers in Figure 1-20: XC7VH870T Banks. For packaging and pinout
information on the Virtex-7 HT devices see www.xilinx.com/member/gtz/index.htm
.
Updated the legend in Figure 3-89, Figure 3-92, Figure 3-93, Figure 3-96, Figure 3-157,
Figure 3-160, Figure 3-161, Figure 3-164, Figure 3-165, and Figure 3-168.
Updated the A and A2 dimensions in Figure 4-11: FF/FFG1156 Flip-Chip BGA Package
Specification for Artix-7 FPGAs, page 225.
Added Note 1 and updated the data in Table 5-1. Updated the Pb-Free Reflow Soldering
in Chapter 5 discussion.
Removed the engineering sample notation from the top mark drawings in Figure 6-1,
Figure 6-2, and Figure 6-3. Updated the L2E description in Table 6-1.
Updated Appendix A.
03/18/2014 1.11 Added the XC7A35T, XC7A50T, and XC7A75T throughout document including
Table 1-3, Table 1-7, Figure 1-1, Figure 1-2, Figure 1-3, Table 2-1, Table 3-1, Table 5-1, and
added or updated Figure 3-1 through Figure 3-28. Also added the automotive XA
Artix-7 FPGA versions (XA7A35T, XA7A50T, XA7A75T, and XA7A100T) and the
defense-graded Artix-7Q device (XQ7A50T) with applicable packages.
In Table 1-1, updated Note 1. In Table 1-11, updated Note 2 and the description of
PUDC_B.
Added links to all the
ruggedized packages in Chapter 2, 7 Series FPGAs Package
Files.
Updated the DCI pin description in the legends for all the Memory Groupings diagrams
in
Chapter 3, Device Diagrams.
Added CPG236 package to document including Figure 4-1, Table 5-1, and Table A-1.
Added CSG325 to document including updating Figure 4-2. This update includes a
change in the A
2
dimensions for the CSG324. Replaced Figure 4-9: FG/FGG484
Wire-bond Fine-Pitch BGA Package Specification for Artix-7 FPGAs, page 223 with a
new drawing with updated dimensions. Replaced Figure 4-10: FG/FGG676 Wire-bond
Fine-Pitch BGA Package Specification for Artix-7 FPGAs, page 224 with a new drawing
with an updated mechanical drawing. Updated the M specification in Figure 4-12: RB484
Ruggedized Flip-Chip BGA Package Specifications for Artix-7 FPGAs, page 226.
Replaced Figure 4-26: FF/FFG676 Flip-Chip BGA Package Specifications for Kintex-7
FPGAs, page 240 with a new drawing where the lid is updated with four corner posts.
Updated the References links in Chapter 5, Thermal Specifications.
Revised the M diameter for FF/FFG, FB/FBG, FH/FHG, FL/FLG, and RF/RB/RS
packages in Table A-1.
Date Version Revision
