ug475_7Series_Pkg_Pinout.pdf

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L XILINX Date Version Revision 7/24/2017 1.15 Added the XC/ XA Spartan-7 devices, the xc7A12T/XA7A12T and XC7A25T/XA7A25T devices, and the CPG238 package Removed the Preface In Chapter 1: Added an Important note on page 22. updated the ddr dqs strobe pin direction in Table 1-12. Added the migrating between Devices section. Updated the CPG236 package on page 41. Corrected the package list in XC7VX485T and XQ7VX485T Banks In Chapter 2: Added Package Specifications Designations section In Chapter 4: Revised Figure 4-47, the RF1761 mechanical drawing In Chapter 5: Added devices to Table 5-1. In Table 5-3, changed the Peak Package Reflow Body Temperature for some packages to 245C In Chapter 6: Added Figure 6-1: Spartan-7 Device Package Marking. Updated Figure 6-2, Figure 6-3, and Figure 6-4 to add the bar code marking and the pb-free character. Added the pb-free character description as outlined in Xcn16022 Cross-ship of Lead-free Bump and Substrates in Lead-free(FFG/FBG/SBG) Packages Revised the bar code section of Table 6-1 to include changes outlined in XcN 16014 Top Marking change for 7 Series, UltraScale, and UltraScale+ Products In Chapter 7: Added packages to Table 7-1 Added Appendix C, Additional Resources and Legal Notices moved the disclaimer Notices and References sections to Appendix C 3/23/2016 1.14 Updated to add the XQ7vX690T in the RF1158 package Added roHs compliant options(FFv packages)where applicable In Table 1-12, updated the SRCC description Updated Figure 4-7 with solder ball composition changes. Refined the A2 dimensions in Figure 4-12 and Figure 4-22. Added the FFv1761 package(Figure 4-42) Added the RF1158 to Figure 4-46 Completely revised Chapter 5, Thermal Specifications with industry standard guidelines for all sections. Updated the thermal management Strategy section Updated the Thermal Interface Material section previously in Appendix B Added the Applied Pressure from Heat Sink to the Package via Thermal Interface Materials section In Appendix B: Moved and renamed the reasons for Thermal Management section to Chapter 5 Removed the Package Loading Specifications section 11/13/2014 1.13 Added XC7A15T and XA7A15T devices throughout the specification 10/28/2014 1.12 Added a discussion on Ula materials on page 17. added clarifications with regards Packages and Note 1 to Table 3-2. Updated Note on page 7 patibility between to Artix-7 devices throughout the document including pin Co In Table 5-2 and Figure 5-7, revised the Peak temperature(body) values and the Ramp-up rate and ramp-down rate to 2 C/s. removed references to CL/Clg packages in Table 5-3 and Appendix A Updated Figure 5-4. Also added the Peak Package Reflow Body Temperature values to Table 5-3. Added Heat Sink Remova Procedure, Package Pressure Handling Capacity, Post Reflow/Cleaning/Washing, and Conformal Coating Added Chapter 7, Packing and Shipping 7 Series FPGAs Packaging UG475(v118)Juy16,2019 www.xilinx.com L XILINX Date Version Revision 3/18/2014 1.11 Added the XC7A35T, XC7A50T, and XC7A75T throughout document including Table 1-3, Table 1-8, Figure 1-6, Figure 1-7, Figure 1-8, Table 2-2, Table 3-2, Table 5-1, and added or updated figure 3-41 through figure 3-80. Also added the automotive XA Artix-7 FPGA versions(XA7A35T, XA7A50T, XA7A75T, and XA7A100T) and the defense-graded Artix-7Q device(XQ7A50T)with applicable packages In Table 1-1, updated note 1 In table 1-12 updated note 2 and the description of UDC B Added links to all the ruggedized packages in Chapter 2, 7 Series FPGAs Package Updated the dCi pin description in the legends for all the memory groupings diagrams in Chapter 3, device diagrams Added CPG236 package to document including Figure 4-7, Table 5-1, and Table A-1 Added CSG325 to document including updating Figure 4-9. This update includes a change in the az dimensions for the CSG324 Replaced Figure 4-16: FG484 and FGG484 Wire-bond Fine-Pitch BGA Package Specification for Artix-7 FPGAs page 276 with a new drawing with updated dimensions Replaced Figure 4-17: FG676 and FGG676 Wire-bond Fine-Pitch BGA Package Specification for Artix-7 FPGAS page 277 with a new drawing with an updated mechanical drawing. Updated the M specification in Figure 4-19: RB484 Ruggedized Flip-Chip BGA Package Specifications for Artix-7 FPGAS, page 279 Replaced Figure 4-33: FF676, FFG676, and FFV676 Flip-Chip BGa Package Specifications for Kintex-7 FPGAs, page 293 with a new drawing where the lid is updated with four corner posts Updated the references links in Chapter 5, Thermal Specifications Revised the m diameter for FF/FFG, FB/FBG, FH/FHG, FL/FLG, and RF/RB/RS packages in table a-1 11/15/2013 1.10 Updated disclaimer Added the xQ devices and rb/RF/RS package information throughout document Added Note 1 to Table 1-2 and note 6 to Table 1-12. revised the super logic region numbers in Figure 1-20 Removed the virtex-7 hT devices(HCG packages). Before removal, revised the super logic region numbers in Figure 1-20: XC7VH870T Banks For packaging and pinout informationonthevirtex-7htdevicesseewww.xilinx.com/member/gtz/index.htr Updated the legend in Figure 3-141, Figure 3-144, Figure 3-145, Figure 3-148 Figure 3-209, Figure 3-212, Figure 3-213, Figure 3-216, Figure 3-217, and Figure 3-220 Updated the a and a2 dimensions in Figure 4-18: FF1156, FFG1156, and FFv1156 Flip-Chip BGA Package Specification for Artix-7 FPGAs, page 278 Added Note 1 and updated the data in Table 5-1. Updated the pb-Free Reflow Soldering in Chapter 5 discussion emoved the engineering sample notation from the top mark drawings in Figure 6-2 Figure 6-3, and Figure 6-4. Updated the l2e description in Table 6-1 Updated Appendix a 7 Series FPGAs Packaging UG475(v118)Juy16,2019 www.xilinx.com L XILINX Date Version Revision 2/14/2013 Clarified pins in Figure 3-89 Updated Figure 4-18 and Figure 4-22 and added Figure 4-23 and Figure 4-24 Revised figure 4-35 and Figure 4-40 In Table 5-1, updated data for Artix-7 FPGAS, XC7K160T FF/FFG/FFV676, Virtex-7T FPGAs and xo7VⅩ1140T Updated Appendix b 10/15/2012 Removed the following devices: XC7A350T, XC7V1500T, XC7VH290T Added Figure 4-26 and updated drawing in Figure 4-27. Added Note 5 to Figure 4-40. Updated A2 dimension in Figure 4-44 Updated the aaa dimension in Figure 4-43 and Figure 4-45 Updated the JEDEC Moisture Sensitivity Level (MSL) for the flip-Chip packages on page 326 7/20/2012 1.7 In Table 1-12, updated the other Pins section Added the XC7VH290T, XC7VH580T, and XC7VH870T and associated HCG packages to all appropriate chapters, tables, and figures Added the SBG484 package for the XC7A200T devices to all appropriate chapters, tables, and figures Updated the XC7VX1140T-FLG1926 headings in Table 2-5, Figure 3-209 through Figure 3-212, and Figure 4-45 Updated GTP Quad numbers in Figure 1-9, Figure 3-74, and Figure 3-78. Also added numbers to Figure 3-77 and figure 3-80. Updated the Xc7V585T-FFG1761 figures Figure 3-137 and Figure 3-140 Added new mechanical drawings for the Artix-7 FPGAs in Chapter 4 along with Figure 4-27, Figure 4-35, and Figure 4-36, and updated Figure 4-35 I n Table 5-1, updated data throughout and added XC7VX1140T(FL1926)and ⅩC7VH580 t data Added Figure 6-2: Artix-7 Device Package Marking 7 Series FPGAs Packaging UG475(v118)Juy16,2019 www.xilinx.com L XILINX Date Version Revision 5/24/2012 Removed the FFG1933 and Flg 1933 packages throughout Added the flg1926 package where approprlate Updated the Introduction in Chapter 1. Updated XC7K420T in Table 1-10. Added Note 7 to Table 1-12. Updated the description and figure in the xc7K420T Banks and XC7VX550T Banks sections Updated Figure 3-86, Figure 3-90, Figure 3-94, and figure 3-34. Added figure 3-209 through figure 3-212 Added Figure 4-14: FB676, FBG676, and FBv676 Flip-Chip Lidless BGA Package Specifications for Artix-7 FPGAs Revised specifications and added capacitor location gures for Figure 4-25: FB676, FBG676, and FBv676 Flip-Chip Lidless bga Package Specifications for Kintex-7 FPGAS Figure 4-28: XC7K325T FB676, FBG676, and FBv676 Die Dimensions with Capacitor Locations Figure 4-29: XC7K41OT FB676, FBG676, and FBv676 Die Dimensions with Capacitor Locations Figure 4-30: FB900, FBG900, and FBv900 Flip-Chip Lidless BGA Package Specifications for Kintex-7 FPGAs Figure 4-31: XC7K325T FB900, FBG900, and FBV900 Die Dimensions with Capacitor Locations Figure 4-32: XC7K410T FB900, FBG900, and FBv900 Die Dimensions with Capacitor Locations Figure 4-37: FF1156, FFG1156, and FFV1156 Flip-Chip bGA Package Specification for Kintex-7 FPGAs Figure 4-40: FF1157, FFG1157, FFV1157, FF1158, FFG1158, and FFV1158 Flip-Chip BGA Package Specification for Virtex-7 FPGAs Added Thermal Management Strategy, Heat Sink Removal Procedure, and updated Soldering Guidelines in Chapter 5 Updated Table A-1 7 Series FPGAs Packaging UG475(v118)Juy16,2019 www.xilinx.com L XILINX Date Version Revision 2/03/2012 Updated Table 1-3 and Table 1-5 and added Table 1-6. Updated Table 1-7 and Table 1-9 and added Table 1-10. Revised Note 2 in Table 1-12 Removed Figures 1-1 and 1-2 along with references to the XC7A8, XC7A15, XC7A30T, and XC7A50T Added Figure 1-10 and Figure 1-3 Clarified Figure 1-14 though Figure 1-17, Figure 1-19, Figure 1-23, and Figure 1-26 Updated Table 2-4 and added Table 2 Added devices to Table 3-2 and revised Table 3-3(XC7K420T and XC7K480T Updated table 3-4 and added table 3-5 and table 3-5 Revised specifications in Figure 4-22: FB484, FBG484, and FBV484(Kintex-7 FPGAs) Flip-Chip LidleSs BGA 1.0 mm Pitch) Figure 4-25: FB676, FBG676, and FBV676(Kintex-7 FPGAs)Flip-Chip Lidless BGa (1.0 mm Pitch) Figure 4-30: FB900, FBG900, and FBv900(Kintex-7 FPGAS)Flip-Chip Lidless BGA 1.0 mm Pitch)and combined with Figure 4-6 igure 4-40: FF1157, FFG1157, FFV1157, FF1158, FFG1158, and FFV1158 (Virtex-7 FPGAs)Flip-Chip BGA (1.0 mm Pitch Added thermal resistance data to Table 5-1 and added the Soldering Guidelines section Added Appendix B 10/17/2011 Revised the FbG484 and FBV484 Package section describing XC7K160T and XA7K160T Banks Added the mechanical drawings: Figure 4-41 and Figure 4-45 Updated Figure 4-44 to include the FF(G)1928 package Added thermal resistance data to table 5-1 10/03/2011 Added Artix-7 device information including updating Table 1-1, adding Table 1-3, Table 1-8 Table 2-2, and Table 3-2 Clarified the interposer in Figure-12 and Figure 1-19. Revised horizontal center for the Xc7VX415T in Figure 1-21. Updated the DXP_0, dXn_o description and notes in Table 1-12. Added devices to the Die Level Bank Numbering Overview section Clarified the I/o banks summary section Added artix-7 device diagrams in the CSG324 package Added Xc7v585T device diagrams Figure 3-133 through Figure 3-140 Moved AD4P/N, AD12P/N, and ADSP/N pins from [IO_L2P_T0_35: I0_L4N_T0_35]to Figure 3-169, Figure 3-173, Figure 3-177, and Figure 3-10/7, Figure 3-165v [O_L1P_TO_35: 0_L3N_T0_35]in Figure 3-141, Figure 3-145 Fixed the labeling for EMCCLK in Figure 3-125, Figure 3-133, Figure 3-141 Figure 3-145, Figure 3-165, Figure 3-169, Figure 3-173, Figure 3-177, and Figure 3-181 Updated the mechanical drawings for figure 4-41 and Figure 4-44 dated thermal resistance data in Table 5-1 Updated chapter 6, package marki 7 Series FPGAs Packaging 7 UG475(v118)Juy16,2019 www.xilinx.com L XILINX Date Version Revision 6/14/201 1.2 Added Virtex-7 device information including updating Table 1-1, adding table 1-3, Table 1-10, Table 2-4, and Table 3-4 In Table 1-12, updated note 3, the Configuration Pins section, and the Analog to Digital Converter(XADC) Pins section pdated Figure 3-99, Figure 3-100, Figure 3-103, Figure 3-104, Figure 3-107 Figure 3-108, Figure 3-111, Figure 3-112, Figure 3-115, Figure 3-116, Figure 3-119, and Figure 3-120. Added Figure 3-120 through Figure 3-184 Added Figure 4-37 the mechanical drawing for the Kintex-7 devices FFG1156 package. Also added some Virtex-7 device mechanical drawings in Figure 4-37 hrough figure 4-44 Added thermal resistance data to table 5-1 4/06/201 1 Removed the SBG324 package from the entire document. Added three Kintex-7 devices:ⅩC7K355T,ⅩC7K420T, and xc7K480T Updated disclaimer and copyright on page 343. Updated package size of FF1156 in Table 1-1. Updated DXP_O, DXN_O in Table 1-12 The Table 2-3 single ascll device files have been updated for both the Xc7K70T and XC7K160T. All ASCll TXT files and the overall ZiP file have been updated on the web Updated the XC7K70TFBG676 figures: Figure 3-101, Figure 3-102, Figure 3-103, and Figure 3-104 Added information to Chapter 4, Mechanical Drawings, Chapter 5, Therma Specifications, and Chapter 6, Package Marking 3/01/2011 1.0 Initial xilinx release 7 Series FPGAs Packaging UG475(v118)Juy16,2019 www.xilinx.com L XILINX Table of contents Chapter 1: Packaging Overview About this guide 16 Introduction.,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,16 Device/Package Combinations and Maximum I/Os n,,.17 Serial Transceiver Channels by Device/Package 19 User I/0 Pins by Device/Package 22 Pin definitions 28 Pin Compatibility between packages 33 Migrating between Devices Die Level Bank Numbering Overview.∴.…,,, 34 nking and clocking Summary 34 XC7S6, XA7S6, XC7S15, and xa7S15 Banks 36 FTGB196 Package 36 CPGA196 Package...,..... 36 CSGA225 Package .36 XC7S25 and xa7525 Banks 37 FTGB196 Package.. 37 CSGA225 Package........ 37 CSGA324 Package 37 XC7S50 and xazs50 Banks 38 FTGB196 Package 38 CSGA324 Package 38 FGGA484 Package 38 XC7S75 XA7S75 XC7S100, and xa7S100 Banks 39 FGGA484 Package 39 FGGA676 Package 39 XC7A12T. XA7A12T. XC7A25T and xa7A25T Banks ,40 G238 Pack CSG325 Package XC7A15T. XC7A35T xAZA15T and xaza35t Banks 41 CPG236 Package 41 FTG256 Package(XC7A15T and XC7 A35T only 41 CSG324 Package 41 CSG325 Package .,,,,,,,,,,41 FGG484 Package(XC7 A15T and XC7A35T only) 41 XC7A50T, XA7A50T, and XQ7A50T Banks 42 CPG236 Package. 42 FTG256 Package(XC7AS0T only) CSG324 Package CSG325 Package 42 FGG484 Package(XC7 A5OT and XQ7A5OT only XC7A75T and xa7a75T Banks 43 FTG256 Package(XC7A75T only) 7 Series FPGAs Packaging Send feedback UG475(v118)Juy16,2019 www.xilinx.com L XILINX CSG324 Package .43 FGG484 Package 43 FGG676 Package(XC7A75T only) ...43 XC7A100T, XQ7A100T, and XA7A100T Banks ...,,,,,,,,,,..44 FTG256 Package(XC7A100T only CSG324 Package FGG484 Package FGG676 Package(XC7A100T only) XC7A200T and xQ7A200T Banks 45 SBG484. SBV484, and rs484 Pack FBG484, FBV484, and rB484 Packages FBG676, FBV676, and RB676 Packages............................... 45 FFG1156 and FFV1156 Package(XC7 A200T only) 45 XC7K7OT Banks 46 FBG484 and FBv484 Package FBG676 and ebv676 Pack 46 XC7K160T and xa7K160T Banks ,,,47 FBG484 and FBv484 Package 47 BG676, FBV676, FFG676, and FFV676 Packa 47 XC7K325T and XQ7K325T Banks 48 FBG676, FBV676, FFG676, FFV676, and rF676 Packages 48 FBG900, FBV900, FFG900, FFV900, and RF900 Packages 48 XC7K355T Bank 49 FFG901 and FFv901 Package 49 XC7K410T and XQ7K410T Banks FBG676, FBV676, FFG676, FFV676, and RF676 P. 50 FBG900, FBV900, FFG900, FFV900, and RF900 Packages 50 ⅩC7K420 T Banks,,,,,,,,,,,, FFG901 and Ffv901 Package 51 FFG1156 and FFV1156 Package ...51 XC7K480T Banks ,,,,52 FFG901 and FFv901 Package FFG1156 and FFV1156 Package 52 XC7V585T and XQ7V585T Banks ..53 FFG1157 and RF1157 Packages FFG1761 and RF1761 Packages XC7V2000 T Banks,,,,,,,,,, 54 FHG1761 Package 4 FLG1925 Package......,..,.... .54 XC內X330 T and Xo內VX30 T Banks....,.......,. ,,,,56 FFG1157, FFV1157, and RF1157 Packages 56 FFG1761, FFV1761, and rf1761 Packages 56 XC7VX415T Banks ...57 FFG1157 and FFV1157 Package 7 FFG1158 and FFV1158 Package ...57 FFG1927 and FFV1927 Package ,,,,,..57 XC7∨X485TandⅪQ內X485 T Banks. ,,,,,58 FFG1157 Package 58 FFG1158 Packages 58 FFG1761 and rF1761 Package 58 FFG1927 Package 58 FFG1930 and RF1930 Packages .58 XC7VX55OT Banks 0 FFG1158 Package......... FFG1927 Package XC7VX690T and xQ7VX690T Banks 61 FFG1157 and RF1157 Packages 7 Series FP(AS RIng 10 UG475(v13 www.xilinx.com

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