Introduction............................................................................................................................... 79
Advantages of VHDL................................................................................................................. 79
Advantages of Verilog...............................................................................................................79
Advantages of SystemVerilog..................................................................................................80
Flip-Flops, Registers, and Latches........................................................................................... 80
Latches........................................................................................................................................83
Tristates...................................................................................................................................... 85
Shift Registers............................................................................................................................87
Dynamic Shift Registers............................................................................................................90
Multipliers.................................................................................................................................. 93
Complex Multiplier Examples.................................................................................................. 96
Pre-Adders in the DSP Block.................................................................................................... 99
Using the Squarer in the UltraScale DSP Block................................................................... 102
FIR Filters..................................................................................................................................104
Convergent Rounding (LSB Correction Technique)............................................................108
RAM HDL Coding Techniques................................................................................................ 113
Inferring UltraRAM in Vivado Synthesis............................................................................... 116
RAM HDL Coding Guidelines..................................................................................................119
Initializing RAM Contents.......................................................................................................154
3D RAM Inference................................................................................................................... 160
Black Boxes.............................................................................................................................. 170
FSM Components.................................................................................................................... 172
ROM HDL Coding Techniques................................................................................................176
Chapter 5: VHDL Support........................................................................................179
Introduction............................................................................................................................. 179
Supported and Unsupported VHDL Data Types..................................................................179
VHDL Objects........................................................................................................................... 183
VHDL Entity and Architecture Descriptions......................................................................... 185
VHDL Combinatorial Circuits................................................................................................. 192
Generate Statements..............................................................................................................193
Combinatorial Processes........................................................................................................195
VHDL Sequential Logic............................................................................................................199
VHDL Initial Values and Operational Set/Reset...................................................................202
VHDL Functions and Procedures...........................................................................................203
VHDL Predefined Packages....................................................................................................205
Defining Your Own VHDL Packages......................................................................................208
VHDL Constructs Support Status...........................................................................................209
UG901 (v2023.1) June 9, 2023
Synthesis 3
