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Xilinx Ultra系列Vivado快速设计技术指南 UG949
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Xilinx Ultra系列Vivado快速设计技术指南 UG949
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UltraFast Design
Methodology Guide for
the Vivado Design Suite
UG949 (v2015.3) November 23, 2015
UltraFast Design Methodology Guide www.xilinx.com 2
UG949 (v2015.3) November 23, 2015
Revision History
The following table shows the revision history for this document.
Date Version Revision
11/23/2015 2015.3
Added
Using IP Core Containers, updated Logic Simulation, added information on
core container files to in
Recommended Source Files to Manage, Minimum Sets of
Source Files to Manage
, and Vivado Design Suite Source Types, added information on
core containers in
Managing IP Sources in Chapter 2, Using the Vivado Design Suite.
Updated Table 3-1, added SLR Utilization Considerations, and added SLR Crossing for
Wide Buses
in Chapter 3, Board and Device Planning.
Updated UltraScale Device Clocking and updated Pipelining Considerations in
Chapter 4, Design Creation.
Added information on report_design_analysis in Clock Skew and Uncertainty
in
Chapter 5, Implementation.
Updated Figure 2-1.
06/01/2015 2015.1
Reorganized and updated
Chapter 2, Using the Vivado Design Suite, including adding
new
Source Management and Revision Control Recommendations section.
Updated I/O Planning Design Flows in Chapter 3, Board and Device Planning.
Reorganized and updated Chapter 4, Design Creation.
Updated Timing Closure in Chapter 5, Implementation, including moving common
design bottlenecks information to the Vivado Design Suite User Guide: Design Analysis
and Closure Techniques (UG906).
Reorganized and updated Chapter 6, Configuration and Debug, including adding
links to various additional resources.
10/14/2014 2014.3
Modified IP Flows related sections. Minor fixes/clarifications based on specific
feedback/suggestions.
04/02/2014 2014.1
Condensed “power” section. Major revamp of “Vivado Design Suite Flows”, and
“Configuration and Debug” chapters. Fixed specific typos, heading name/levels and
minor changes.
12/18/2013 2013.4
Removed checklist appendix. These links have been replaced with a checklist version
that is available in Documentation Navigator.
11/25/2013 2013.3
Fixed errors in table of contents.
10/27/2013 2013.3
Fixed incorrect hyperlinks.
10/23/2013 2013.3
Initial Xilinx release.
Send Feedback
UltraFast Design Methodology Guide www.xilinx.com 3
UG949 (v2015.3) November 23, 2015
Table of Contents
Chapter 1: Introduction
About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Guide Applicability and References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Need for Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Design Methodology Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Rapid Validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Accessing Documentation and Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 2: Using the Vivado Design Suite
Overview of Using the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Vivado Design Suite Use Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Configuring IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Creating IP Subsystems with IP Integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Packaging Custom IP and IP Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Creating Custom Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Logic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Synthesis, Implementation, and Design Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Source Management and Revision Control Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Upgrading Designs and IP to the Latest Vivado Design Suite Release . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 3: Board and Device Planning
Overview of Board and Device Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PCB Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Clock Resource Planning and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O Planning Design Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
FPGA Power Aspects and System Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Worst Case Power Analysis Using Xilinx Power Estimator (XPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 4: Design Creation
Overview of Design Creation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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UltraFast Design Methodology Guide www.xilinx.com 4
UG949 (v2015.3) November 23, 2015
Defining a Good Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
RTL Coding Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Clocking Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Working With Intellectual Property (IP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Working with Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Chapter 5: Implementation
Overview of Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Synthesis Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Bottom Up Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Moving Past Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Implementing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Timing Closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Chapter 6: Configuration and Debug
Overview of Configuration and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Appendix A: Baselining and Timing Constraints Validation Procedure
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Appendix B: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Send Feedback
UltraFast Design Methodology Guide www.xilinx.com 5
UG949 (v2015.3) November 23, 2015
Chapter 1
Introduction
About This Guide
Xilinx
®
programmable devices have capacities of multi-million Logic Cells (LC), and
integrate an ever-increasing share of today’s complex electronic systems, including:
•Embedded subsystems
• Analog and digital processing
• High-speed connectivity
• Network processing
In order to create such complex systems within short design cycles, designers synthesize
many large blocks of logic from RTL, and reuse Intellectual Property (IP) modules from Xilinx
or third parties.
Given the complexity of this process, it is critical to adopt a set of best practices collectively
called the UltraFast™ Design Methodology, a set of best practices that maximize
productivity for both system integration and design implementation.
Guide Contents
This guide discusses a design methodology process to follow in order to achieve an
efficient and quicker design implementation, and to derive the maximum value from Xilinx
devices and tools.
In most cases, this guide tells you the reasoning behind its recommendations. By
understanding that reasoning, you can appreciate the potential consequences of deviating
from the recommended methodology, and take appropriate precautions.
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