硬件描述语言实验四位全加器

-- Quartus II VHDL Template
-- Basic Shift Register
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity zz is
  
 port 
 (
  A,B  : in std_logic_vector(3 downto 0);
  Ci : in std_logic;
  S :out std_logic_vector(3 downto 0);
  Co : out std_logic
 );
end entity;
architecture struct of zz is
component adder is
port(
  a,b,ci:in std_logic;
  s,co:out std_logic
);
end component adder;
signal c0,c1,c2:std_logic;  
begin
u1:adder port map(A(0),B(0),ci,S(0),c0);
u2:adder port map(A(1),B(1),c0,S(1),c1);
u3:adder port map(A(2),B(2),c1,S(2),c2);
u4:adder port map(A(3),B(3),c2,S(3),co);
end architecture struct;
library ieee;