FPGA部分动态重配置教程和实例工程

This archive contains the Color2 design for the Partial Reconfiguration User Guide. This design has been updated for ISE 14.5 released on 03 April 2013. This revision corresponds to the 14.5 User Guide design documented in UG702. The design has been completely implemented one time. The PlanAhead directory contains the PlanAhead project and all completed Configurations. The Synth directory contains the synthesis results from the scripted runs. The Implementation directory is prepared for running the Tcl scripts to implement the full design. The sample Tcl scripts can be found in the Tools directory. To execute the scripts for full synthesis and place and route for all configurations, run the following command from the Implementation directory: xtclsh ..\Tools\xpartition.tcl ..\Tools\data.tcl Synthesis or implementation phases only can be run for all configurations by replacing data.tcl in the above command by data_synth.tcl or data_impl.tcl, respectively. � Copyright 2002 � 2013 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws. DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.