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TLE4473G V55-2 英飞凌芯片 INFINEON 中文版规格书手册.pdf
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TLE4473G V55-2 英飞凌芯片 INFINEON 中文版规格书手册
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Type Package Marking
TLE 4473 GV55-2 PG-DSO-12-11 (RoHS compliant) TLE4473 GV55-2
Dual Low Dropout Voltage Regulator
TLE 4473 GV55-2
PG-DSO-12-11
Data Sheet 1 Rev. 1.2, 2008-10-28
Features
• Stand-by output 190 mA; 5 V ± 2%
• Main output: 300 mA, 5 V
tracked to the stand-by output
• Low quiescent current consumption
• Disable function separately for both outputs
• Wide operation range: up to 42 V
• Very low dropout voltage
• 2 independent reset circuits
• Watchdog
• Output protected against short circuit
• Wide temperature range: -40 °C to 150 °C
• Overtemperature protection
• Overload protection
• Green product (RoHS compliant)
• AEC qualified
Functional Description
The TLE 4473 is a monolithic integrated voltage regulator with two low dropout outputs,
a main output Q1 for loads up to 300 mA and a stand by output Q2 providing a maximum
of 190 mA. The stand-by regulator transforms an input voltage
V
I
in the range of 5.6 V ≤
V
I
≤ 42 V to an output voltage of V
Q2
= 5.0 V (±2%). The main output is tracked to the
stand by output voltage and provides also 5 V. A versions of this device with 5 V/3.3 V
and 5 V/2.6 V are also available, please refer to the data sheet TLE 4473 G V53/
TLE 4473 G V52. The Inhibit input INH1 disables the output Q1 only, whereas Inhibit
input INH2 disables both, Q1 and Q2 output. The quiescent current then is 1 µA.
The TLE 4473 is designed to supply microprocessor systems and sensors under the
severe conditions of automotive applications and therefore is equipped with additional
protection functions against overload, short circuit and overtemperature. The device
operates in the wide junction temperature range of -40 °C to 150 °C.
Data Sheet 2 Rev. 1.2, 2008-10-28
TLE 4473 GV55-2
The device features a reset with adjustable power on delay for each of the outputs. In
addition the output for the microcontroller supply comes up with a watchdog in order to
supervise a connected microcontroller
Reset and Watchdog Behavior
The reset output RO2 is in high-state if the voltage on the delay capacitor
C
D2
is greater
or equal
V
DU2
. The delay capacitor C
D2
is charged with the current I
DC2
for output
voltages greater than the reset threshold
V
RT2
. If the output voltage gets lower than V
RT2
(‘reset condition’) a fast discharge of the delay capacitor C
D2
sets in and as soon as V
D2
gets lower than V
DL2
the reset output RO2 is set to low-level. The time for the delay
capacitor charge is the reset delay time. For the power-on case the charging process of
C
D2
starts from 0 V, which leads to the equation:
(1)
for the power-on reset delay time.
When the voltage on the delay capacitor has reached
V
DU2
and reset was set to high, the
watchdog circuit is enabled and discharges
C
D2
with the constant current I
DD2
.
If there is no rising edge observed at the watchdog input,
C
D2
will be discharge down to
V
DL2
. Then reset output RO2 will be set to low and C
D2
will be charged again with the
current
I
DC2
until V
D2
reaches V
DU2
and reset will be set high again.
If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge
period
C
D2
is charged again and the reset output stays high. After V
D2
has reached V
DU2
,
the periodical cycle starts again.
The watchdog timing is shown in Figure 1. The maximum duration between two
watchdog pulses corresponds to the minimum watchdog trigger time
T
WI,tr
. Higher
capacitances on pin D2 result in longer watchdog trigger times:
(2)
If the output voltage Q1 decreases below
V
RT1
(typ. 4.65 V), the external capacitor C
D1
is discharged by the reset generator of the main output. If the voltage on this capacitor
drops below
V
DL1
, a reset signal is generated on pin 2 (RO1). If the output voltage rises
above the reset threshold,
C
D1
will be charged with the constant current I
DC1
. After the
power-on-reset time the voltage on the capacitor reaches
V
DU1
and the reset output will
be set high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of
C
D1
using the above given equation (1) analogous for
Q1.
t
Don,
C
D2
V
DU2
×
I
DC2
-----------------------------=
T
WI,tr
max
0.34 ms/nF C
D2
×=
TLE 4473 GV55-2
Data Sheet 3 Rev. 1.2, 2008-10-28
Figure 1 Watchdog Timing Schedule
AED03099_4473
W
V
V
V
Q
D2
V
V
RO2
V
DU2
-
V
DL2
()
Ι
(
DC2
+
DD2
)
Ι
Ι
DC2
Ι
x
DD2
T
WD, p
=
WD, L
t
WD, p
T
WI, tr
T
WD, L
t
=
VV
(
DU2
-
DL2
)
Ι
DC2
T
=
VV
(
DU2
-
DL2
)
Ι
DD2
DU2
V
V
DL2
Ι
Ι
WI, tr
C
D2
;
;
D2
C
D2
C
t
t
t
t
t
Data Sheet 4 Rev. 1.2, 2008-10-28
TLE 4473 GV55-2
Figure 2 Block Diagram with Typical External Components
TLE 4473 GV55-2
TLE4473G V55-2_BLOCKDIAG RAM.VSD
Current and
Saturation
Control,
Overcurrent
Protection
Overtemperature
Shutdown
Bandgap
Reference
Inhibit
Reset
Generator
Watchdog
Current and
Saturation
Control,
Overcurrent
Protection
Inhibit
Reset
Generator
GND
10
µF
4.7 k
Ω
4
3
Q2
RO2
µC
Sup ply
µC
Reset
1WI Watchdog
(fro m µC )
100 nF
11D2
2RO1
6Q1
10
µF
4.7 k
Ω
e.g. Senso
r
Sup ply
e.g. Senso
r
Reset
(to µC )
INH18
µC
INH29
Ignition
I7
V
Bat
C
I
100 nF
12
100 nF
10D1
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