Lattice Semiconductor Table of Contents
IPUG82_01.5, December 2011 3 Tri-Rate SDI PHY IP User’s Guide
VPID Extraction.......................................................................................................................................... 29
10-bit Mode for SD Rx................................................................................................................................ 29
Clock Enable Port ...................................................................................................................................... 29
Custom Format Tab ............................................................................................................................................ 29
Custom Format Support for HD ................................................................................................................. 30
Custom Format Support for 3G.................................................................................................................. 30
Value or Range .......................................................................................................................................... 30
EAV2SAV cycles- Value ............................................................................................................................ 30
EAV2SAV Cycles- Minimum ...................................................................................................................... 31
EAV2SAV Cycles- Maximum ..................................................................................................................... 31
SAV2EAV Cycles- Value............................................................................................................................ 31
SAV2EAV Cycles- Minimum ...................................................................................................................... 31
SAV2EAV Cycles- Maximum ..................................................................................................................... 31
Advanced Tab ..................................................................................................................................................... 31
3G/HD/SDProgram Time ........................................................................................................................... 31
Lock Match Threshold................................................................................................................................ 31
Unlock Error Threshold .............................................................................................................................. 31
Chapter 4. IP Core Generation............................................................................................................. 32
Licensing the IP Core.......................................................................................................................................... 32
Getting Started .................................................................................................................................................... 32
IPexpress-Created Files and Top Level Directory Structure............................................................................... 35
Running Functional Simulation ........................................................................................................................... 37
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 37
Hardware Evaluation........................................................................................................................................... 38
Enabling Hardware Evaluation in Diamond................................................................................................ 38
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 38
Updating/Regenerating the IP Core .................................................................................................................... 38
Regenerating an IP Core in Diamond ........................................................................................................ 38
Regenerating an IP Core in ispLEVER ...................................................................................................... 39
Chapter 5. Application Support........................................................................................................... 40
Tri-Rate SDI PHY IP Loopback and Passthrough Sample Designs ................................................................... 40
Loopback Design ....................................................................................................................................... 40
Passthrough Design............................................................................................................................................ 41
Simulating the Sample Design ............................................................................................................................ 42
Testbench and Configuration File .............................................................................................................. 43
Implementing and Testing the Sample Design ................................................................................................... 45
Board Switch Assignments for Sample Designs ........................................................................................ 45
Transmitter Testing .................................................................................................................................... 46
Receiver Testing ........................................................................................................................................ 46
LCD Display ............................................................................................................................................... 47
Loopback Testing....................................................................................................................................... 47
Passthrough Testing .................................................................................................................................. 47
Chapter 6. Core Verification ................................................................................................................ 48
Chapter 7. Support Resources ............................................................................................................ 49
Lattice Technical Support.................................................................................................................................... 49
Online Forums............................................................................................................................................ 49
Telephone Support Hotline ........................................................................................................................ 49
E-mail Support ........................................................................................................................................... 49
Local Support ............................................................................................................................................. 49
Internet ....................................................................................................................................................... 49
References.......................................................................................................................................................... 49
Lattice Tri-Rate SDI PHY IP Website......................................................................................................... 49
SMTPE Website......................................................................................................................................... 49
