TI-DS100BR210.pdf资源-CSDN文库

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《TI-DS100BR210：超低功耗10.3 Gbps双通道重定时器》 TI的DS100BR210是一款专为高速数据传输设计的超低功耗、高性能的双通道重定时器。这款器件支持的数据速率高达10.3 Gbps，适用于构建高速串行链接。其独特的特性使其在以太网转接驱动领域具有显著优势。 DS100BR210的引脚配置为两个单向通道，每个通道都能独立处理数据传输。输入端配备了一个强大的4级连续时间线性均衡器（CTLE），该均衡器能够在5 GHz时提供高达+36 dB的增益，有效抵消因板级走线或双轴同轴电缆等互联介质引起的符号间干扰(ISI)，从而开启闭合的输入眼图，保证信号质量。在发射端，DS100BR210集成了可编程的输出去加重驱动器，能够提供最大-12 dB的去加重，并且可以根据需要调整输出电压水平，范围从700 mVp-p到1300 mVp-p。此外，它还提供了传输电压摆幅控制（VOD Control），允许用户在700至1300 mVp-p之间进行设置，确保信号在长距离传输中的稳定性。为了兼容10G-KR双向接口，DS100BR210支持后向通道通信和训练，使得KR主机和终端设备可以通过802.3ap以太网标准定义的后向通信技术调整发送和接收均衡器系数，优化整个链路性能。这种高级信号调理功能显著提高了链路的稳定性和可靠性。该器件采用单一电源电压，可选择2.5 V或3.3 V，降低了系统供电的复杂性。同时，为了方便配置，DS100BR210提供了通过引脚选择、EEPROM或SMBus接口的可编程选项，使用户能够灵活地根据具体应用需求进行设定。此外，DS100BR210的4 mm × 4流经式引脚布局有助于简化PCB设计，降低系统集成难度。其低至65 mW/通道（典型值）的功耗和选项关闭未使用的通道功能，进一步提升了能效。 TI的DS100BR210是一款针对高速以太网应用的理想选择，结合了低功耗、高性能、灵活配置以及兼容多种通信标准的特性，为现代网络基础设施提供了高效且可靠的解决方案。

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IN+

IN-

IDLE DETECT

OUTBUF

SMBus

VOD/ DE-EMPHASIS CONTROL

VDD

SMBus

Tx IDLE Enable

DEM

EQ[1:0]

OUT+

OUT-

50:50:

VOD

SMBus

LOS

Channel

Status

and

Control

SD_TH

TX_DIS

MODE

Line Card

2x10G

ASIC

FPGA

2x10G

2 x SFP+

(Stacked)

DS100BR210

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

DS100BR210

SNLS348E –OCTOBER 2011–REVISED JANUARY 2015

DS100BR210 Ultra Low Power 10.3 Gbps 2-Channel Repeater

with Input Equalization and Output De-Emphasis

1 Features 3 Description

The DS100BR210 is an extremely low power, high

• Two Channel Repeaters for up to 10.3 Gbps

performance repeater designed to support serial links

– DS100BR210 : 2x Unidirectional Channels

with data rates up to 10.3 Gbps. The DS100BR210

– DS100BR111 : 1x Bidirectional Lane

pinout is configured as two unidirectional channels.

The DS100BR210 inputs feature a powerful 4-stage

• 10G-KR Bi-directional Interface Compatibility

continuous time linear equalizer (CTLE) to provide a

– Allows for Back-channel Communication and

boost of up to +36 dB at 5 GHz and open an input

Training

eye that is completely closed due to inter-symbol

• Low 65 mW/channel (Typical) Power

interference (ISI) induced by the interconnect

Consumption, with Option to Power Down Unused

mediums such as board traces or twin-axial copper

cables. The transmitter features a programmable

Channels

output de-emphasis driver with up to -12 dB and can

• Advanced Signal Conditioning Features

drive output voltage levels from 700 mVp-p to 1300

– Receive Equalization up to +36 dB

mVp-p.

– Transmit De-emphasis up to -12 dB

When configured as a 10G-KR repeater, the

– Transmit VOD Control: 700 to 1300 mVp-p

DS100BR210 allows the KR host and the end point to

optimize the full link by adjusting transmit and receive

– Low Residual DJ at 10.3 Gbps

equalizer coefficients using back-channel

• Programmable Via Pin Selection, EEPROM, or

communication techniques specified by the 802.3ap

SMBus Interface

Ethernet standard.

• Single Supply Voltage: 2.5 V or 3.3 V

The programmable settings can be applied via pin

• Flow-thru Pinout in 4 mm × 4 mm 24-pin Leadless

control, SMBus protocol, or an external EEPROM. In

WQFN Package

the EEPROM mode, the configuration information is

• 5 kV HBM ESD Rating

automatically loaded on power up, thereby eliminating

the need for an external microprocessor or software

• -40 to 85°C Operating Temperature Range

driver.

2 Applications

Device Information

(1)

• High-speed Active Copper Cable Modules and

PART NUMBER PACKAGE BODY SIZE (NOM)

FR-4 Backplane in Communication Systems

DS100BR210 WQFN (24) 4.00 mm x 4.00 mm

• 10GE, 10G-KR, FC, SAS, SATA 3/6 Gbps (with

(1) For all available packages, see the orderable addendum at

OOB Detection), InfiniBand, CPRI, RXAUI and

the end of the datasheet.

many others

4 Simplified Schematic

Typical Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS100BR210

SNLS348E –OCTOBER 2011–REVISED JANUARY 2015

www.ti.com

Table of Contents

8.3 Feature Description................................................. 13

1 Features.................................................................. 1

8.4 Device Functional Modes........................................ 13

2 Applications ........................................................... 1

8.5 Programming........................................................... 15

3 Description ............................................................. 1

8.6 Register Maps......................................................... 29

4 Simplified Schematic............................................. 1

9 Application and Implementation ........................ 36

5 Revision History..................................................... 2

9.1 Application Information............................................ 36

6 Pin Configuration and Functions......................... 3

9.2 Typical Application ................................................. 37

7 Specifications......................................................... 6

10 Power Supply Recommendations ..................... 44

7.1 Absolute Maximum Ratings ...................................... 6

10.1 3.3-V or 2.5-V Supply Mode Operation................. 44

7.2 ESD Ratings ............................................................ 6

10.2 Power Supply Bypass ........................................... 45

7.3 Recommended Operating Conditions....................... 6

11 Layout................................................................... 45

7.4 Thermal Information.................................................. 6

11.1 Layout Guidelines ................................................. 45

7.5 Electrical Characteristics........................................... 7

11.2 Layout Example .................................................... 45

7.6 Electrical Characteristics — Serial Management Bus

12 Device and Documentation Support ................. 47

Interface .................................................................... 9

12.1 Documentation Support ........................................ 47

7.7 Timing Requirements — LOS and ENABLE /

DISABLE Timing ........................................................ 9

12.2 Trademarks........................................................... 47

7.8 Typical Characteristics............................................ 11

12.3 Electrostatic Discharge Caution............................ 47

8 Detailed Description............................................ 12

12.4 Glossary................................................................ 47

8.1 Overview ................................................................. 12

13 Mechanical, Packaging, and Orderable

8.2 Functional Block Diagram ....................................... 12

Information ........................................................... 47

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (April 2013) to Revision E Page

• Added, updated, or renamed the following sections: Device Information Table, Application and Implementation;

Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and

Ordering Information .............................................................................................................................................................. 1

• Added Thermal Information ................................................................................................................................................... 6

Product Folder Links: DS100BR210

DS100BR210

SNLS348E –OCTOBER 2011 –REVISED JANUARY 2015

www.ti.com

Pin Functions

(1)

(continued)

I/O, TYPE DESCRIPTION

NAME NUMBER

ENSMB = Float or 1 (SMBus MODES)

I, 2-LEVEL, Clock output when loading EEPROM configuration, reverting to SMBus clock input

LVCMOS, when EEPROM load is complete (ALL_DONE = 0).

SCL 5

O, Open External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode)

Drain recommended as per SMBus interface standards

(2)

I, 2-LEVEL, In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output.

LVCMOS, External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode)

SDA 4

O, Open recommended as per SMBus interface standards

(2)

Drain

ENSMB Master or Slave mode

I, 4-LEVEL, SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus

AD0-AD3 10, 9, 2, 1

LVCMOS slave address inputs. There are 16 addresses supported by these pins.

Pins must be tied Low or High when used to define the device SMBus address.

(3)

ENSMB = Float: When using SMBus Master Mode, a logic low on this pin starts the

load from the external EEPROM.

I, 2-LEVEL,

READEN 17 ENSMB = 1: When using SMBus Slave Mode, the VOD_SEL/READEN pin must be

LVCMOS

tied Low for the AD[3:0] to be active. If this pin is tied High or left floating, an address

of 0xB0 will be used for the DS100BR210.

When using an External EEPROM (ENSMB = Float), Valid Register Load Status

O, 2-LEVEL, Output

DONE 18

LVCMOS High = External EEPROM load failed or incomplete

Low = External EEPROM load passed

ENSMB = 0 (PIN MODE)

EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. EQA[1:0]

controls the A channel, and EQB[1:0] controls the B channel. The pins are only active

EQA0, EQA1 10, 9 I, 4-LEVEL, when ENSMB = 0.

EQB0, EQB1 1, 2 LVCMOS When ENSMB = 1, the SMBus registers provide independent control of each channel,

and the EQB0/B1 pins are converted to SMBus AD2/AD3 inputs.

See Table 3 for additional information.

DEMA and DEMB control the level of de-emphasis for the output driver when in 10G

mode. DEMA controls the A channel, and DEMB controls the B channel. The pins are

I, 4-LEVEL, only active when ENSMB = 0.

DEMA, DEMB 4, 5

LVCMOS When ENSMB = 1, the SMBus registers provide independent control of each channel,

and the DEM pins are converted to SMBus SCL and SDA pins.

See Table 4 for additional information.

VOD Select

High = 10G-KR Mode (VOD = 1.1 Vpp or 1.3 Vpp)

I, 4-LEVEL, Float = (VOD = 1.0 Vpp)

VOD_SEL 17

LVCMOS 20 kΩ to GND = (VOD = 1.2 Vpp)

1 kΩ to GND = (VOD = 700 mVpp)

See for additional notes. See Table 2 for additional information.

Controls Device Mode of Operation

High= 10GbE Mode, Continuous Talk (Output Always On)

I, 4-LEVEL, Float = 10G-KR Mode, Slow OOB

MODE 18

LVCMOS 20 kΩ to GND = eSATA Mode, Fast OOB, Auto Low Power on 100 µs of inactivity. SD

stays active.

1 kΩ to GND = SAS Mode, Fast OOB

CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)

I, 2-LEVEL, High = OUTA Disabled, OUTB Disabled

TX_DIS 6

LVCMOS Low = OUTA and OUTB Enabled

O, Open Indicates Loss of Signal (Default is LOS on INA). Can be modified via SMBus

LOS 13

Drain registers.

The SD_TH pin controls LOS threshold setting

Assert (mVpp), Deassert (mVpp)

I, 4-LEVEL, High = 190 mVpp, 130 mVpp

SD_TH 14

LVCMOS Float = 180 mVpp, 110 mVpp (Default)

20 kΩ to GND = 160 mVpp, 100 mVpp

1 kΩ to GND = 210 mVpp, 150 mVpp

(4)

(2) SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5 V mode or 3.3 V mode.

(3) Setting VOD_SEL = High in SMBus Mode will force the SMBus Address = 0xB0

(4) Using values less than the default level can extend the time required to detect LOS and are not recommended.

Product Folder Links: DS100BR210

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