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TI-DS100RT410是一款专为以太网设计的低功耗10 Gigabit Ethernet (10GbE) 四通道重定时器。这款设备的主要目标是解决高速串行数据传输中遇到的问题，如信号衰减、噪声和串扰，以确保在长距离或高干扰环境下数据的稳定传输。 1. **特性**： - **独立通道锁定**：每个通道可以独立地锁定到10.3125Gbps的数据速率，支持10GbE和1GbE标准。 - **低延迟**：大约300ps的延迟，有利于保持高速数据流的同步。 - **自适应均衡**：内置连续时间线性均衡器(CTLE)能适应不同的信道条件，提升信号质量，最大增益可达34dB在5GHz频率下。 - **时钟和数据恢复(CDR)**：用于锁定输入信号并恢复数据，即使在信号质量下降的情况下也能保证数据的准确传输。 - **可调节参数**：包括发送电压过驱动(VOD)和发送去加重(DE)，可调范围分别为600至1300mVp-p和高达-12dB。 - **片上眼图监视器(EOM)**：实时监测信号质量，辅助系统调优。 - **伪随机二进制序列(PRBS)发生器**：用于进行误码率(BER)测试，确保在比特误差率低于1×10^-15的高水平性能。 - **自校准抽头判决反馈均衡器(DFE)**：适用于应对高串扰环境，优化信号恢复。 - **系统管理总线(SMBus)**：通过I2C接口进行配置，便于系统集成和参数设置。 - **工作温度范围**：在-40°C至85°C之间，确保在各种环境下的可靠性。 - **封装形式**：7mm × 7mm的48引脚超薄四方扁平无引线(WQFN)封装，易于安装和布局。 2. **应用场景**： - **以太网交换机和线路卡**：在交换机的背板和中间平面中，DS100RT410能延长数据传输距离，减少信号损失。 - **光学模块**：与SFP+ (SFF8431)光学模块配合，支持铜缆和直连铜缆连接。 - **中继器与重定时器的升级**：设备间可通过引脚兼容性实现无缝升级，比如从DS100RT410升级到带DFE功能的型号。 3. **产品系列**： - **不同数据速率**：除了DS100RT410支持10.3125Gbps，还有其他型号如DS110RT410、DS110DF410等，覆盖8.5Gbps至12.5Gbps的速率范围，满足不同应用场景的需求。 - **功能扩展**：一些型号如DS100DF410和DS110DF410，除了基本的均衡、CDR和DE，还包含了DFE功能，提供更高级的信号恢复能力。 4. **编程**： - **配置模式**：可以通过SMBus (I2C)接口或外部EEPROM加载进行参数配置，适应不同应用需求。总结来说，TI-DS100RT410是一款高性能的10GbE重定时器，它通过先进的信号处理技术，如自适应均衡、时钟和数据恢复、眼图监视器等功能，有效提升了高速以太网通信的稳定性和可靠性。这款器件不仅适用于数据中心、电信网络等场合，还便于系统设计者根据具体需求进行灵活配置和升级。

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DS100DF410

Passive Copper

ASIC

DS100DF410

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SFP+(SFF8431)

QSFP

DS100DF410

10GbE

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DS100RT410

ZHCSEC0A –JANUARY 2013–REVISED OCTOBER 2015

DS100RT410 低低功功耗耗 10GbE 四四通通道道重重定定时时器器

1 特特性性 2 应应用用

• 每个通道独立锁定至

• 前端口 SFF 8431 (SFP+) 光学铜缆和直连铜缆

10.3125Gbps

• 背板长度延长，数据重定时器

• 锁定操作（通常低于 15ms）

• 以太网：10GbE、1GbE

• 低延迟（约 300ps）

如需其他数据传输速率和数据传输协议，可使用重

定时器系列的其他引脚兼容器件。

• 具有自适应均衡功能，可在 5GHz 频率下提供最高

34dB 的升压

3 说说明明

• 可调节的发送 V

：600 至 1300mVp-p

DS100RT410 是一款具有集成信号调节功能的四通道

• 可调节发送去加重功能：最高达 -12dB

重定时器。每条通道的数据传输速率均可独立锁定至

• 典型功耗（均衡 (EQ) + 动态范围控制 (DRC) + 去

加重 (DE)）：

10.3125Gbps，从而支持 10GbE。该器件包含完全自

150mW/通道

适应性连续时间线性均衡器 (CTLE)、时钟和数据恢复

• 可编程的输出极性反转

(CDR) 以及发送去加重 (DE) 驱动器，可在有损且存在

• 输入信号检测，CDR 锁定检测和指示器

串扰的高速串行链路中实现数据传输，比特误差率

• 片上眼图监视器 (EOM)，伪随机二进制序列

(BER) < 1 × 10

-15

。 DS100RT410 器件具有自校准 5

(PRBS) 发生器

抽头判决反馈均衡器 (DFE)，是串扰较为严重的信道的

• 2.5V±5% 单电源

理想选择。

• 系统管理总线 (SMbus) 和电可擦除可编程只读存储

该器件能够轻松实现可编程设置，既可通过 SMBus

器 (EEPROM) 配置模式

(I2C) 接口进行应用，也可通过外部 EEPROM 加载。

• 工作温度范围：-40°C 至 85°C

凭借片上眼图监视器和 PRBS 发生器，可以在系统调

• 7mm × 7mm 48 引脚超薄四方扁平无引线 (WQFN)

通或现场调试过程中实时测量高速串行数据。

封装

DS100RT410 采用直通引脚和单电源，因此易于使

• 可轻松在中继器与重定时器之间进行引脚兼容升级

用。

– DS100RT410 (EQ + CDR +

DE)：10.3125Gbps

器器件件信信息息

(1)

– DS100DF410 (EQ + DFE + CDR + DE)：

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

10.3125Gbps

DS100RT410 WQFN (48) 7.00mm x 7.00mm

– DS110RT410 (EQ + CDR + DE)：8.5Gbps 至

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

11.3Gbps

– DS110DF410 (EQ + DFE + CDR +

典典型型应应用用图图

DE)：8.5Gbps 至 11.3Gbps

– DS125RT410 (EQ + CDR + DE)：9.8Gbps 至

12.5Gbps

– DS125DF410 (EQ + DFE + CDR + DE)：

9.8Gbps 至 12.5Gbps

– DS100BR410 (EQ + DE)：最高为

10.3125Gbps

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS448

DS100RT410

ZHCSEC0A –JANUARY 2013–REVISED OCTOBER 2015

www.ti.com.cn

目目录录

7.5 Programming........................................................... 16

1 特特性性.......................................................................... 1

7.6 Register Maps......................................................... 28

2 应应用用.......................................................................... 1

8 Application and Implementation ........................ 45

3 说说明明.......................................................................... 1

8.1 Application Information............................................ 45

4 修修订订历历史史记记录录 ........................................................... 2

8.2 Typical Application .................................................. 45

5 Pin Configuration and Functions......................... 3

9 Power Supply Recommendations...................... 47

6 Specifications......................................................... 5

10 Layout................................................................... 47

6.1 Absolute Maximum Ratings ..................................... 5

10.1 Layout Guidelines ................................................. 47

6.2 ESD Ratings.............................................................. 5

10.2 Layout Example .................................................... 47

6.3 Recommended Operating Conditions ...................... 5

11 器器件件和和文文档档支支持持 ..................................................... 49

6.4 Thermal Information.................................................. 5

11.1 文档支持................................................................ 49

6.5 Electrical Characteristics........................................... 6

11.2 社区资源................................................................ 49

6.6 Typical Characteristics.............................................. 8

11.3 商标 ....................................................................... 49

7 Detailed Description .............................................. 9

11.4 静电放电警告......................................................... 49

7.1 Overview ................................................................... 9

11.5 Glossary................................................................ 49

7.2 Functional Block Diagram ......................................... 9

12 机机械械、、封封装装和和可可订订购购信信息息....................................... 50

7.3 Feature Description................................................... 9

7.4 Device Functional Modes........................................ 12

4 修修订订历历史史记记录录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (January 2013) to Revision A Page

• 已添加

器件信息

表，ESD

额定值

表，

热性能信息

表，

详细说明

部分，

应用和实施

部分，

电源相关建议

部分，

布局

部

分，

器件和文档支持

部分以及

机械、封装和可订购信息

部分 .................................................................................................. 1

• Changed Channel Register 33 to Reserved. ....................................................................................................................... 39

TOP VIEW

RXN3

VDD

RXN2

VDD

RXN1

VDD

RXN0

TXN3

GND

TXN2

GND

TXP1

TXN0

RXP1

VDD

RXP2

RXP3 TXP3

TXP2

GND

1RXP0

TXP0

TXN1

DS100RT410

DAP = GND

LPF_CP_ 3

LPF_REF_3

VDD

LOCK_3ADDR_3

SDC

SDA

REFCLK_IN

EN_SMB

LOCK_2/ADDR_2

GND

LPF_REF_2

LPF_CP_ 2

7 mm x 7 mm, 0.5 mm pitch

LPF_REF_1

LPF_CP_ 1

GND

LOCK_1/ADDR_1

ALL_DONE

REFCLK_OUT

INT

READ_EN

LOCK_0/ADDR_0

VDD

LPF_REF_0

LPF_CP_ 0

DS100RT410

www.ti.com.cn

ZHCSEC0A –JANUARY 2013–REVISED OCTOBER 2015

5 Pin Configuration and Functions

RHS Package

48 Pin WQFN

Top View

Pin Functions

I/O, TYPE

(1)

DESCRIPTION

NAME NO.

HIGH-SPEED DIFFERENTIAL I/O

RXP0 1 Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal

I, CML

RXN0 2 differential input impedance = 100 Ω. Must be AC coupled.

RXP1 4 Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal

I, CML

RXN1 5 differential input impedance = 100 Ω. Must be AC coupled.

RXP2 8 Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal

I, CML

RXN2 9 differential input impedance = 100 Ω. Must be AC coupled.

RXP3 11 Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal

I, CML

RXN3 12 differential input impedance = 100 Ω. Must be AC coupled.

TXP0 36 Inverting and non-inverting CML-compatible differential outputs from the driver.

O, CML

TXN0 35 Nominal differential output impedance = 100 Ω. Must be AC coupled.

TXP1 33 Inverting and non-inverting CML-compatible differential outputs from the driver.

O, CML

TXN1 32 Nominal differential output impedance = 100 Ω. Must be AC coupled.

TXP2 29 Inverting and non-inverting CML-compatible differential outputs from the driver.

O, CML

TXN2 28 Nominal differential output impedance = 100 Ω. Must be AC coupled.

TXP3 26 Inverting and non-inverting CML-compatible differential outputs from the driver.

O, CML

TXN3 25 Nominal differential output impedance = 100 Ω. Must be AC coupled.

(1) Notes: I = Input, O = Output and 2.5-V LVCMOS pins are 2.5-V levels only.

Only SMBus pins SDA and SDC and INT pin are 3.3-V tolerant. These three pins are open-drain and require external pullup

resistors.

DS100RT410

ZHCSEC0A –JANUARY 2013–REVISED OCTOBER 2015

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE

(1)

DESCRIPTION

NAME NO.

LOOP FILTER CONNECTION PINS

LPF_CP_0 47 Loop filter connection

I/O, analog

LPF_REF_0 48 Place a 22 nF ± 10% capacitor between LPF_CP_0 and LPF_REF_0

LPF_CP_1 38 Loop filter connection

I/O, analog

LPF_REF_1 37 Place a 22 nF ± 10% capacitor between LPF_CP_1 and LPF_REF_1

LPF_CP_2 23 Loop filter connection

I/O, analog

LPF_REF_2 24 Place a 22 nF ± 10% capacitor between LPF_CP_2 and LPF_REF_2

LPF_CP_3 14 Loop filter connection

I/O, analog

LPF_REF_3 13 Place a 22 nF ± 10% capacitor between LPF_CP_3 and LPF_REF_3

REFERENCE CLOCK I/O

Input is 2.5 V, 25 MHz ± 100-ppm reference clock from external oscillator.

REFCLK_IN 19 I, 2.5-V analog

No stringent phase noise requirement

Output is 2.5 V, buffered replica of reference clock input for connecting multiple

REFCLK_OUT 42 O, 2.5-V analog

DS100RT410 devices on a board

LOCK INDICATOR PINS

LOCK_0 45

Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding

LOCK_1 40 O, 2.5-V

channel.

LOCK_2 21 LVCMOS

These pins are shared with SMBus address strap input functions read at start-up.

LOCK_3 16

SMBus MASTER MODE PINS

O, 2.5-V Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM read has

ALL_DONE 41

LVCMOS been completed.

Input is 2.5 V, a transition from high to low starts the load from the external EEPROM.

READ_EN 44 I, 2.5-V LVCMOS

The READ_EN pin must be tied low when in SMBus slave mode

INTERRUPT OUTPUT

Used to signal horizontal or vertical eye opening out of tolerance, loss of signal detect,

O, 3.3-V

or CDR unlock

INT 43 LVCMOS, Open

External 2-kΩ to 5-kΩ pullup resistor is required.

Drain

Pin is 3.3-V LVCMOS tolerant.

SERIAL MANAGEMENT BUS (SMBus) INTERFACE

ADDR_0 Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer.

ADDR_1 These pins are strap inputs. Their state is read on power-up to set the SMBus address

ADDR_2 I, 2.5-V LVCMOS in SMBus control mode.

ADDR_3 High = 1-kΩ to VDD, Low = 1-kΩ to GND

These pins are shared with the lock indicator functions. See Table 2.

Input is 2.5 V, selects SMBus master mode or SMBus slave mode

EN_SMB = High for slave mode

EN_SMB 20 I, 2.5-V analog

EN_SMB = Float for master mode

Tie READ_EN pin low for SMBus slave mode. See Table 1.

I/O, 3.3-V Data Input and Open Drain Output

SDA 18 LVCMOS, Open External 2-kΩ to 5-kΩ pullup resistor is required.

Drain Pin is 3.3-V LVCMOS tolerant.

I/O, 3.3-V Clock Input / Open Drain Clock Output

SDC 17 LVCMOS, Open External 2-kΩ to 5-kΩ pullup resistor is required.

Drain Pin is 3.3-V LVCMOS tolerant.

POWER

3, 6, 7,

Power V

= 2.5 V ± 5%

10, 15, 46

22, 27,

GND 30, 31, Power Ground reference.

34, 39

Ground reference. The exposed pad at the center of the package must be connected

DAP PAD Power to ground plane of the board with at least 4 vias to lower the ground impedance and

improve the thermal performance of the package.

DS100RT410

www.ti.com.cn

ZHCSEC0A –JANUARY 2013–REVISED OCTOBER 2015

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN MAX UNIT

Supply Voltage (V

) –0.5 2.75 V

2.5 I/O Voltage (LVCMOS and Analog) –0.5 2.75 V

3.3 LVCMOS I/O Voltage (SDA, SDC, INT) –0.5 4.0 V

Signal Input Voltage (RXPn, RXNn) –0.5 2.75 V

Signal Output Voltage (TXPn, TXNn) –0.5 2.75 V

Junction Temperature 150 °C

Storage Temperature, T

stg

–65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT

Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all

±6000

pins

(1)

(ESD)

Electrostatic discharge Machine Model (MM), STD - JESD22-A115-A

(2)

±250 V

Charged Device Model (CDM), per JEDEC specification JESD22-

±1250

C101, all pins

(3)

(1) JEDEC document JEP155 states that 6000-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V MM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 1250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage (V

to GND) 2.375 2.5 2.625 V

Ambient temperature –40 25 85 °C

6.4 Thermal Information

See

(1)

DS100RT410

THERMAL METRIC

(2)

RHS (WQFN) UNIT

48 PINS

θJA

Junction-to-ambient thermal resistance 29.2 °C/W

θJC(top)

Junction-to-case (top) thermal resistance 10.2 °C/W

θJB

Junction-to-board thermal resistance 6.3 °C/W

Junction-to-top characterization parameter 0.1 °C/W

Junction-to-board characterization parameter 6.3 °C/W

θJC(bot)

Junction-to-case (bottom) thermal resistance 2.0 °C/W

(1) No airflow, 4-layer JEDEC, 9 thermal vias

(2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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