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TI-LM5070.pdf
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TI-LM5070.pdf
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![](https://csdnimg.cn/release/download_crawler_static/87045131/bg1.jpg)
RJ45
Connector
TX+ (1)
TX- (2)
RX+ (3)
RX- (6)
(4)
(7)
(5)
(8)
To PHY
To PHY
Hot Plug Controller
In-rush and Fault
Current Limiting
DC-DC
Converter
Controller
Current Mode
IEEE 802.3af
Interface
UVLO
Signature Detection
Classification
LM5070
VDC
LM5070
www.ti.com
SNVS308G –OCTOBER 2004–REVISED APRIL 2013
LM5070 Integrated Power Over Ethernet PD Interface and PWM Controller
Check for Samples: LM5070
1
FEATURES
DESCRIPTION
The LM5070 power interface port and pulse width
2
• Fully Compliant 802.3af Power Interface Port
modulation (PWM) controller provides a complete
• 80V, 1Ω, 400 mA Internal MOSFET
integrated solution for Powered Devices (PD) that
• Programmable Inrush Current Limit
connect into Power over Ethernet (PoE) systems. The
LM5070 integrates an 80V, 400mA line connection
• Detection Resistor Disconnect Function
switch and associated control for a fully IEEE 802.3af
• Programmable Classification Current
compliant interface with a full featured current mode
• Programmable Under-voltage Lockout with
pulse width modulator dc-dc converter. All power
Programmable Hysteresis
sequencing requirements between the controller
interface and switch mode power supply (SMPS) are
• Thermal Shutdown Protection
integrated into the IC. Two options are available
• Current Mode Pulse Width Modulator
providing either an 80% maximum duty cycle limit
• Supports Both Isolated and Non-Isolated
with slope compensation (on the –80 suffix) device or
Applications
a 50% maximum duty cycle limit and no slope
compensation on the (–50 suffix) device.
• Error Amplifier and Reference for Non-Isolated
Applications
PACKAGES
• Programmable Oscillator Frequency
• TSSOP-16
• Programmable Soft-Start
• WSON-16 (5 mm x 5 mm)
• 80% Maximum Duty Cycle Limiter, Slope
Compensation (-80 device)
• 50% Maximum Duty Cycle Limiter, No Slope
Compensation (-50 device)
• 800 mA Peak Gate Driver
Block Diagrams
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
![](https://csdnimg.cn/release/download_crawler_static/87045131/bg2.jpg)
RSIG
RCLASS
UVLO
UVLORTN
RCLP
V
EE
RTN
V
IN
RT
CS
COMP
FB
V
CC
OUT
SS
ARTN
14
13
12
11
10
8 9
15
16
1
2
3
4
5
7
6
V
EE
LM5070
OUT
V
IN
V
CC
CS
RTN
ARTN
RCLASS
RCLP
V
IN
+3.3V
RSIG
5V
FB
V
EE
Internal
High Voltage
Regulator
V
IN
< 10V
Switch
Bandgap
Regulator
SMPS
Controller
COMP
SS
RT
Programmable
Inrush Current
LM5070
SNVS308G –OCTOBER 2004–REVISED APRIL 2013
www.ti.com
Figure 1. Simplified Block Diagram and Application
Connection Diagram
Figure 2. 16 Lead TSSOP/WSON
See Package Number PW or NHQ0016A
2 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5070
![](https://csdnimg.cn/release/download_crawler_static/87045131/bg3.jpg)
LM5070
www.ti.com
SNVS308G –OCTOBER 2004–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin Name Description Application Information
1 V
IN
System high potential input. The diode “OR” of several lines entering the PD, it is the more positive
input potential.
2 RSIG Signature resistor pin. Connect a 25kΩ signature resistor from V
IN
to this pin for signature
detection.
3 RCLASS Classification resistor pin. Connect the classification programming resistor from this pin to V
EE
.
4 UVLO Line under-voltage lockout. An external resistor divider from V
IN
to UVLORTN programs the
shutdown levels with a 2.00V threshold at the UVLO pin. Hysteresis is
set by a switched internal 10uA current source that forces additional
current into the resistor divider.
5 UVLORTN Return for the external UVLO resistors. Connect the bottom resistor of the resistor divider between the UVLO
pin and this pin.
6 RCLP Current limit programming pin. Programs the inrush current limit for the device. If left open, the inrush
current limit will default to 400mA max.
7 V
EE
System low potential input. Diode “OR’d” to the RJ45 connector and PSE’s –48V supply, it is the
more negative input potential.
8 RTN System return for the PWM converter. The drain of the internal current limiting power MOSFET which
connects V
EE
to the return path of the dc-dc converter.
9 OUT Output of the PWM controller. DC-DC converter gate driver output with 800mA peak sink current
capability.
10 V
CC
Output of the internal high voltage series When the auxiliary transformer winding (if used) raises the voltage on
pass regulator. Regulated output voltage is this pin above the regulation set point, the internal series pass regulator
nominally 7.8V. will shutdown, reducing the controller power dissipation.
11 FB Feedback signal. Inverting input of the internal error amplifier. The non-inverting input is
internally connected to a 1.25V reference.
12 COMP The output of the error amplifier and input COMP pull-up is provided by an internal 5K resistor which may be used
to the Pulse Width Modulator. to bias an opto-coupler transistor.
13 CS Current sense input. Current sense input for current mode control and over-current
protection. Current limiting is accomplished using a dedicated current
sense comparator. If the CS pin voltage exceeds 0.5V the OUT pin
switches low for cycle-by-cycle current limiting. CS is held low for 50ns
after OUT switches high to blank leading edge current spikes.
14 RT / SYNC Oscillator timing resistor pin and An external resistor connected from RT to ARTN sets the oscillator
synchronization input. frequency. This pin will also accept narrow ac-coupled synchronization
pulses from an external clock.
15 SS Soft-start input. An external capacitor and an internal 10uA current source set the soft-
start ramp rate.
16 ARTN Analog PWM supply return. RTN for sensitive analog circuitry including the SMPS current limit
amplifier.
— EP Exposed PAD, underside of the WSON Internally bonded to the die substrate. Connect to V
EE
potential for low
package option. thermal impedance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM5070
![](https://csdnimg.cn/release/download_crawler_static/87045131/bg4.jpg)
LM5070
SNVS308G –OCTOBER 2004–REVISED APRIL 2013
www.ti.com
Absolute Maximum Ratings
(1)(2)
V
IN
,RTN to V
EE
-0.3V to 80V
RSIG to V
IN
-12V to 0V
UVLO to V
EE
-0.3V to 57V
UVLORTN -0.3V to 13V
RCLASS, RCLP to V
EE
-0.3V to 7V
ARTN to RTN -0.3V to 0.3V
V
CC
, OUT to ARTN -0.3V to 16V
All other inputs to ARTN -0.3V to 7V
ESD Rating Human Body Model 2000V
Storage Temperature -65°C to +150°C
Junction Temperature 150°C
Lead Temperature
(3)
Wave (4 seconds) 260°C
Infrared (10 seconds) 240°C
Vapor Phase (75 seconds) 219°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. The
absolute maximum rating of V
IN
, RTN to V
EE
is derated to (-0.3V to 76V) at -40°C.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For detailed information on soldering plastic TSSOP and WSON packages, see the Packaging Databook available from TI.
Operating Ratings
V
IN
voltage 1.8V to 75V
External voltage applied to V
CC
8.1V to 15V
Operating Junction Temperature -40°C to +125°C
Electrical Characteristics
(1)
Specifications in standard type face are for T
J
= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: V
IN
= 48V, V
CC
= 10V, RT = 30.3kΩ.
Symbol Parameter Conditions Min Typ Max Units
Powered Interface
IOS Offset Current V
IN
< 10.0V 10 uA
VCLSS(ON) Signature Resistor Disable / V
IN
with respect to V
EE
10.0 11.5 12.5 V
Classification Current Turn On
VCLSS(OFF) Classification Current Turn Off V
IN
with respect to V
EE
20.5 22.0 23.0 V
Classification Voltage With respect to V
EE
1.43 1.5 1.57 V
ICLASS Supply Current During V
IN
=17V 0.5 1.0 mA
Classification
IDC Supply Current During Normal OUT floating 1 1.9 mA
Operation
UVLO Pin Reference Voltage V
IN
> 12V 1.95 2.00 2.05 V
UVLO Hysteresis Current V
IN
> UVLO 8.0 10 11.5 uA
Softstart Release RTN falling with respect to 1.2 1.45 1.7 V
V
EE
Softstart Release Hysteresis RTN rising with respect to 0.8 1.1 1.3 V
V
EE
RDS(ON) PowerFET Resistance I = 350mA, 1 2.2 Ω
V
IN
= 48V
ILEAK SMPS Bias Current V
EE
= 0V, V
IN
= RTN = 57V 100 uA
ILIM Default Current Limit V
EE
= 0V, RTN = 3.0V, 350 390 420 mA
Temp = 0°C to 85°C
(1) Min and Max limits are 100% production tested at 25 °C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
4 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5070
![](https://csdnimg.cn/release/download_crawler_static/87045131/bg5.jpg)
LM5070
www.ti.com
SNVS308G –OCTOBER 2004–REVISED APRIL 2013
Electrical Characteristics
(1)
(continued)
Specifications in standard type face are for T
J
= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: V
IN
= 48V, V
CC
= 10V, RT = 30.3kΩ.
Symbol Parameter Conditions Min Typ Max Units
ILIM Default Current Limit V
EE
= 0V, RTN = 3.0V, 325 390 420 mA
Temp = -40°C to 125°C
Current Limit Programming V
EE
= 0V, RTN = 3.0V, -20 +20 %
Accuracy RCLP = 80.6kΩ
Startup Regulator
VccReg V
CC
Regulation Open ckt 7.5 7.8 8.1 V
V
CC
Current Limit See
(2)
15 20 mA
V
CC
Supply
V
CC
UVLO (Rising) VccReg – VccReg –
300mV 100mV
V
CC
UVLO (Falling) 5.9 6.25 6.6 V
Supply Current (Icc) Cload = 0 1.5 3 mA
Error Amplifier
GBW Gain Bandwidth 4 MHz
DC Gain 75 dB
Input Voltage FB = COMP 1.219 1.281 V
1.212 1.288
COMP Sink Capability FB=1.5V COMP=1V 5 20 mA
Current Limit
ILIM Delay to Output CS step from 0 to 0.6V, 20 ns
time to onset of OUT
transition (90%)
Cycle by Cycle Current Limit 0.44 0.5 0.56 V
Threshold Voltage
Leading Edge Blanking Time 55 ns
CS Sink Impedance (clocked) 25 55 Ω
Softstart
Softstart Current Source 7 10 13 uA
Oscillator
(3)
Frequency1 175 200 225 KHz
(RT = 30.3K)
Frequency2 505 580 665 KHz
(RT = 10.5K)
Sync threshold 3.1 3.8 V
PWM Comparator
Delay to Output COMP set to 2V 25 ns
CS stepped 0 to 0.4V, time
to onset of OUT transition
low
Min Duty Cycle COMP=0V 0 %
Max Duty Cycle (-80 Device) 80 %
Max Duty Cycle (-50 Device) 50 %
COMP to PWM Comparator Gain 0.33
COMP Open Circuit Voltage 4.5 5.4 6.3 V
COMP Short Circuit Current COMP= 0V 0.6 1.1 1.5 mA
Slope Compensation
Slope Comp Amplitude Delta increase at PWM 105 mV
(LM5070-80 Device Only) Comparator to CS
(2) Device thermal limitations may limit usable range.
(3) Specification applies to the oscillator frequency. The operational frequency of the LM5070-50 devices is divided by two.
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM5070
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