TI-UCC21530-Q1.pdf

UCC21530-Q1 4-A, 6-A, 5.7-kV

RMS

Isolated Dual-Channel Gate Driver

with 3.3-mm Channel-to-Channel Spacing

1 Features

• AEC-Q100 qualified with:

– Device temperature grade 1

– Device HBM ESD classification level H2

– Device CDM ESD classification level C6

• Functional Safety Quality-Managed

• Switching parameters:

– 19-ns typical propagation delay

– 10-ns minimum pulse width

– 5-ns maximum delay matching

– 6-ns maximum pulse-width distortion

• Common-mode transient immunity (CMTI) greater

than 100-V/ns

• Isolation barrier life >40 years

• 4-A peak source, 6-A peak sink output

• TTL and CMOS compatible inputs

• Operating temperature range –40 to +125°C

• Safety-related certifications:

– 8000-V

PK

isolation per DIN V VDE V

0884-11 :2017-01

– 5.7-kV

– CSA certification per IEC 60950-1, IEC

62368-1, IEC 61010-1 and IEC 60601-1 end

equipment standards

• AC-to-DC and DC-to-DC power delivery

• Energy storage systems

(1)

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (November 2018) to Revision C (March 2019) Page

• Initial release.......................................................................................................................................................1

Changes from Revision C (March 2019) to Revision D (April 2021) Page

• Added 8-V UVLO option to features, description, and device information sections .......................................... 1

• Added information to pin 7 in Pin function table................................................................................................. 3

• Added VDE certification, CSA master contract, and CQC certificate numbers to Safety-Related Certifications

table ................................................................................................................................................................... 7

• Added 8-V UVLO thresholds to EC table ...........................................................................................................8

PIN

I/O

DESCRIPTION

NAME NO.

DT 6 I

DT pin configuration:

• Tying DT to VCCI disables the DT feature and allows the outputs to overlap.

• Placing a resistor (R

) between DT and GND adjusts dead time according to the

GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground.

INA 1 I

Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

INB 2 I

Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

NC 7 – No internal connection. This pin can be left floating, tied to VCCI, or tied to GND.

OUTA 15 O Output of driver A. Connect to the gate of the A channel FET or IGBT.

OUTB 10 O Output of driver B. Connect to the gate of the B channel FET or IGBT.

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