TI-UC2875-EP.pdf资源-CSDN文库

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SGLS233A − FEBRUARY 2004 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Extended Temperature Performance of

−25°C to 110°C

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product Change Notification

D Qualification Pedigree

†

D Zero to 100% Duty Cycle Control

D Programmable Output Turn-On Delay

D Compatible with Voltage or Current Mode

Topologies

D Practical Operation at Switching

Frequencies to 1 MHz

D Four 2 A Totem Pole Outputs

D 10 MHz Error Amplifier

D Under-Voltage Lockout

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D Low Startup Current −150 mA

D Outputs Active Low During UVLO

D Soft-Start Control

D Latched Over-Current Comparator With Full

Cycle Restart

D Trimmed Reference

description/ordering information

The UC2875 integrated circuit implements control of a bridge power stage by phase-shifting the switching of

one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination

with resonant, zero-voltage switching for high efficiency performance at high frequencies. This circuit may be

configured to provide control in either voltage or current mode operation, with a separate over-current shutdown

for fast fault protection.

A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay,

providing time to allow the resonant switching action, is independently controllable for each output pair (A−B,

C−D).

ORDERING INFORMATION

PACKAGE

‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−25°C to 110°C SOP − DW Tape and reel UC2875SDWREP UC2875SEP

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DW PACKAGE

(TOP VIEW)

NC = No Connect

VREF

E/AOUT

EA−

EA+

CS+

SOFTSTART

GND

DELAYSET C−D

OUTD

OUTC

GND

RAMP

SLOPE

CLOCKSYNC

FREQSET

DELAYSET A−B

GND

OUTA

OUTB

PWRGND

VIN

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   



SGLS233A − FEBRUARY 2004 − REVISED DECEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†‡

Supply voltage (VC, VIN) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (sink or source), I

DC 0.50 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulse (0.5 µs)

3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog I/O voltage −0.3 V to 5.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating jucntion temperature range, T

−55_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 300_C. . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals.

electrical characteristics, T

= −25_C to 110_C, VC = VIN = 12 V, R

FREQSET

= 12 kW, C

FREQSET

= 330 pF,

SLOPE

= 12 kW, C

RAMP

= 200 pF, C

DELAYSET

A−B

= C

DELAYSET

C−D

= 0.01 mF,

DELAYSET

A−B

= I

DELAYSET

C−D

= −500 mA, and T

= T

(unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Undervoltage Lockout

Start threshold 10.75 11.75 V

UVLO hysteresis 0.5 1.25 2 V

Supply Current

Supply current, I

startup VIN = 8 V, VC = 20 V, R

SLOPE

open, I

DELAY

= 0 150 600 µA

Supply current, I

startup VIN = 8 V, VC = 20 V, R

SLOPE

open, I

DELAY

= 0 10 100 µA

Supply current, I

30 44 mA

Supply current, I

15 30 mA

Voltage Reference

Output voltage T

= 25_C 4.92 5 5.08 V

Line regulation voltage VIN = 11 V to 20 V 1 10 mV

Load regulation voltage I

VREF

= −10 mA 5 20 mV

Total variation Line, Load, Temperature 4.9 5.1 V

Noise voltage 10 Hz to 10 kHz 50 µVrms

Long term stability 1000 hours, T

= 125_C 2.5 mV

Short circuit current VREF = 0 V, T

= 25_C 60 mA

Error Amplifier

Offset voltage 5 15 mV

Input bias current 0.6 3 µA

Open loop voltage gain (A

VOL)

E/AOUT

= 1 V to 4 V 60 90 dB

Common mode rejection ratio (CMRR) V

= 1.5 V to 5.5 V 75 95 dB

PSRR VIN = 11 V to 20 V 85 100 dB

Output sink current V

E/AOUT

= 1 V 1 2.5 mA

Output source current V

E/AOUT

= 4 V −1.3 −0.5 mA

High-level output voltage (V

) I

E/AOUT

= −0.5 mA 4 4.7 5 V

Low-level output voltage (V

) I

E/AOUT

= 1 mA 0 0.5 1 V

Unity gain bandwidth 7 11 MHz

Slew rate 6 11 V/µsec

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