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###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 4.2
## \ \ Application : MIG
## / / Filename : readme.txt
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Steps to run simulations using Modelsim/QuestaSim,
## Cadence IES, and Synopsys VCS
## Assumptions : Simulations are run in \sim folder of MIG output "Open IP
## Example Design" directory
## Reference :
## Revision History:
###############################################################################
MIG outputs script files required to run the simulations for Modelsim/QuestaSim,
Vivado Simulator, IES and VCS. These scripts are valid only for running
simulations for "Open IP Example Design"
1. How to run simulations in Modelsim/QuestaSim simulator
A) sim.do File :
a) The 'sim.do' file has commands to compile and simulate memory
interface design and run the simulation for specified period of time.
b) It has the syntax to Map the required libraries (unisims_ver,
unisim and secureip). The libraries should be mapped using
the following command
vmap unisims_ver <unisims_ver lib path>
vmap unisim <unisim lib path>
vmap secureip <secureip lib path>
Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file
c) Displays the waveforms that are listed with "add wave" command.
B) Steps to run the Modelsim/QuestaSim simulation:
a) The user should invoke the Modelsim/QuestaSim simulator GUI.
b) Change the present working directory path to the sim folder.
In Transcript window, at Modelsim/QuestaSim prompt, type the following
command to change directory path.
cd <sim directory path>
c) Run the simulation using sim.do file.
At Modelsim/QuestaSim prompt, type the following command:
do sim.do
d) To exit simulation, type the following command at Modelsim/QuestaSim
prompt:
quit -f
e) Verify the transcript file for the memory transactions.
2. How to run simulations in Vivado simulator
A) Following files are provided :
a) The 'xsim_run.bat' is the executable file for Vivado simulator under
MicroSoft Windows environment.
b) The 'xsim_run.sh' is the executable file for Vivado simulator under
Linux environment.
c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and
simulate memory interface design and run the simulation for specified
period of time.
d) xsim_options.tcl file has commands to add waveforms and simulation
period.
e) xsim_files.prj file has list of rtl files for simulating the design.
f) $XILINX_VIVADO environment variable must be set in order to compile
glbl.v file
B) Steps to run the Vivado Simulator simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using xsim_run.sh file under Linux environment and
xsim_run.bat under MicroSoft Windows environment.
c) Verify the transcript file for the memory transactions.
3. How to run Cadence IES Simulations
A) ies_run.sh File :
a) The "ies_run.sh" file contains the commands for simulation of the
hdl files.
b) Libraries must be mapped before running simulations. Following
procedure must be followed to before running simulations
1. Create two files named cds.lib and hdl.var in this directory
2. Create a directory 'worklib' in same directory.
mkdir worklib
3. Add following lines in the cds.lib file to map Xilinx libraries
DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim
DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver
DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip
DEFINE worklib ./worklib
4. ATTENTION: In above lines replace the path for libraries as per your
compiled Xilinx libraries directory
5. ATTENTION: Add the lines in the same order given above
6. Please make sure you need to map all Xilinx libraries mentioned above
7. Save and close the cds.lib file
Also, $XILINX_VIVADO environment variable must be set in order to
compile glbl.v file and the above mentioned library files
B) Steps to run the IES simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using ies_run.sh file. Type the following command:
./ies_run.sh
c) Verify the ies_sim.log file for the memory transactions.
4. How to run Synopsys VCS Simulations
A) vcs_run.sh Fi
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『FPGA通信接口』DDR(3)DDR3颗粒读写测试 (2000个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
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__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
xsim_run.bat 3KB
xsim_run.bat 3KB
xsim_run.bat 3KB
xsim_run.bat 3KB
elaborate.bat 1KB
simulate.bat 942B
compile.bat 844B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
bd_9054.bd 26KB
design_1.bd 5KB
bd_6f02.bd 2KB
bd_6f02.bd 2KB
design_1.bda 3KB
bd_6f02.bda 2KB
ddr3_four_top.bit 10.91MB
dimm_top.bit 10.91MB
ddr4_top.bit 4.57MB
bd_9054.bmm 730B
design_1.bxml 2KB
bd_6f02.bxml 602B
xsim_15.c 2.63MB
MT40A1G16075E.csv 782B
waveform.csv 249B
xsim.dbg 1.74MB
xsim.dbg 1KB
ddr4_top_routed.dcp 15.55MB
ddr4_top_placed.dcp 13.06MB
ddr3_four_top_routed.dcp 9.07MB
dimm_top_routed.dcp 8.99MB
ddr4_top_opt.dcp 8.4MB
ddr3_four_top_placed.dcp 7.49MB
dimm_top_physopt.dcp 7.43MB
dimm_top_placed.dcp 7.43MB
ddr4_0.dcp 6.28MB
ddr4_0.dcp 6.21MB
ddr4_0.dcp 6.2MB
ddr4_0.dcp 6.2MB
ddr4_0.dcp 6.2MB
ddr3_four_top_opt.dcp 5.75MB
dimm_top_opt.dcp 5.71MB
design_1_mig_7series_0_1.dcp 4.62MB
design_1_mig_7series_0_1.dcp 4.62MB
mig_7series_0.dcp 4.06MB
mig_7series_0.dcp 4.06MB
mig_7series_0.dcp 4.05MB
mig_7series_0.dcp 4.04MB
mig_7series_0.dcp 4.04MB
mig_JC.dcp 3.21MB
mig_JC.dcp 2.69MB
ddr4_0_phy.dcp 1.58MB
ddr4_0_phy.dcp 1.58MB
ddr4_0_phy.dcp 1.58MB
ddr4_0_phy.dcp 1.58MB
ila_0.dcp 1.03MB
ila_0.dcp 1.03MB
ila_0.dcp 1.02MB
ila_0.dcp 1023KB
ila_0.dcp 722KB
dbg_hub.dcp 371KB
dbg_hub.dcp 345KB
ddr3_four_top.dcp 245KB
dimm_top.dcp 229KB
ddr4_top.dcp 154KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
waveform.dmp 491B
compile.do 9KB
compile.do 9KB
compile.do 9KB
compile.do 9KB
compile.do 9KB
compile.do 9KB
compile.do 9KB
compile.do 9KB
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