###############################################################################
## (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 4.2
## \ \ Application : MIG
## / / Filename : readme.txt
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Steps to run simulations using Modelsim/QuestaSim,
## Cadence IES, and Synopsys VCS
## Assumptions : Simulations are run in \sim folder of MIG output "Open IP
## Example Design" directory
## Reference :
## Revision History:
###############################################################################
MIG outputs script files required to run the simulations for Modelsim/QuestaSim,
Vivado Simulator, IES and VCS. These scripts are valid only for running
simulations for "Open IP Example Design"
1. How to run simulations in Modelsim/QuestaSim simulator
A) sim.do File :
a) The 'sim.do' file has commands to compile and simulate memory
interface design and run the simulation for specified period of time.
b) It has the syntax to Map the required libraries (unisims_ver,
unisim and secureip). The libraries should be mapped using
the following command
vmap unisims_ver <unisims_ver lib path>
vmap unisim <unisim lib path>
vmap secureip <secureip lib path>
Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file
c) Displays the waveforms that are listed with "add wave" command.
B) Steps to run the Modelsim/QuestaSim simulation:
a) The user should invoke the Modelsim/QuestaSim simulator GUI.
b) Change the present working directory path to the sim folder.
In Transcript window, at Modelsim/QuestaSim prompt, type the following
command to change directory path.
cd <sim directory path>
c) Run the simulation using sim.do file.
At Modelsim/QuestaSim prompt, type the following command:
do sim.do
d) To exit simulation, type the following command at Modelsim/QuestaSim
prompt:
quit -f
e) Verify the transcript file for the memory transactions.
2. How to run simulations in Vivado simulator
A) Following files are provided :
a) The 'xsim_run.bat' is the executable file for Vivado simulator under
MicroSoft Windows environment.
b) The 'xsim_run.sh' is the executable file for Vivado simulator under
Linux environment.
c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and
simulate memory interface design and run the simulation for specified
period of time.
d) xsim_options.tcl file has commands to add waveforms and simulation
period.
e) xsim_files.prj file has list of rtl files for simulating the design.
f) $XILINX_VIVADO environment variable must be set in order to compile
glbl.v file
B) Steps to run the Vivado Simulator simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using xsim_run.sh file under Linux environment and
xsim_run.bat under MicroSoft Windows environment.
c) Verify the transcript file for the memory transactions.
3. How to run Cadence IES Simulations
A) ies_run.sh File :
a) The "ies_run.sh" file contains the commands for simulation of the
hdl files.
b) Libraries must be mapped before running simulations. Following
procedure must be followed to before running simulations
1. Create two files named cds.lib and hdl.var in this directory
2. Create a directory 'worklib' in same directory.
mkdir worklib
3. Add following lines in the cds.lib file to map Xilinx libraries
DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim
DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver
DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip
DEFINE worklib ./worklib
4. ATTENTION: In above lines replace the path for libraries as per your
compiled Xilinx libraries directory
5. ATTENTION: Add the lines in the same order given above
6. Please make sure you need to map all Xilinx libraries mentioned above
7. Save and close the cds.lib file
Also, $XILINX_VIVADO environment variable must be set in order to
compile glbl.v file and the above mentioned library files
B) Steps to run the IES simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using ies_run.sh file. Type the following command:
./ies_run.sh
c) Verify the ies_sim.log file for the memory transactions.
4. How to run Synopsys VCS Simulations
A) vcs_run.sh Fi
没有合适的资源?快使用搜索试试~ 我知道了~
温馨提示
内容名称:DDR3(APP/Naive 接口)工程代码 工程环境:Xilinx VIVADO 2018.3 内容概要:使用 Xilinx VIVADO 中的 MIG IP 核,读写位宽设置为 128 比特,并设计了外部读写模块 Verilog 代码,直接对 Xilinx 定义的 APP 接口进行操作。本工程已经过 Testbench 测试无误,并已将仿真所需的头文件 ddr3_model_parameters.vh 和 DDR3 仿真模块文件 ddr3_model.sv 添加进工程中,读者下载后能直接进行仿真。本工程的建立、代码实现原理、仿真测试讲解等已在博客主页文章中进行展示,以便于读者理解。 适合人群:FPGA(VIVADO)使用者,掌握 Verilog。 阅读建议:结合主页博客讲解进行阅读。
资源详情
资源评论
资源推荐
收起资源包目录
Xilinx DDR3 工程代码(APP 接口) (1081个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
_info 49KB
_info 18KB
_info 8KB
_info 680B
_info 137B
_info 137B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
xsim.ini.bak 23KB
xsim_run.bat 3KB
elaborate.bat 926B
compile.bat 846B
simulate.bat 825B
compile.bat 819B
simulate.bat 810B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
xsim_11.c 1.21MB
xsim_11.c 1.21MB
.cxl.modelsim.nt64.cmd 671B
.cxl.verilog.secureip.secureip.nt64.cmf 7KB
.cxl.systemverilog.secureip.secureip.nt64.cmf 844B
xsim.dbg 1.38MB
xsim.dbg 1.38MB
mig_7series_0.dcp 2.66MB
mig_7series_0.dcp 2.66MB
mig_7series_0.dcp 2.65MB
mig_7series_0.dcp 2.42MB
ddr3_rw_top.dcp 2.25MB
mig_7series_0.dcp 1.91MB
mig_7series_0.dcp 1.91MB
ddr3_data_fifo.dcp 166KB
ddr3_data_fifo.dcp 166KB
ddr3_data_fifo.dcp 165KB
clk_wiz_fifo.dcp 9KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
tb_ddr3_rw_top_compile.do 10KB
ddr3_rw_top_compile.do 10KB
compile.do 9KB
compile.do 9KB
compile.do 8KB
compile.do 8KB
sim.do 7KB
compile.do 1KB
compile.do 985B
compile.do 971B
compile.do 744B
compile.do 687B
compile.do 663B
tb_ddr3_rw_top_simulate.do 629B
compile.do 622B
ddr3_rw_top_simulate.do 617B
compile.do 612B
simulate.do 347B
simulate.do 347B
simulate.do 347B
tb_ddr3_rw_top_wave.do 347B
ddr3_rw_top_wave.do 344B
simulate.do 312B
simulate.do 311B
simulate.do 311B
simulate.do 311B
simulate.do 306B
simulate.do 306B
elaborate.do 219B
simulate.do 205B
simulate.do 203B
simulate.do 195B
elaborate.do 184B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
xsimk.exe 9.49MB
xsimk.exe 9.46MB
run.f 9KB
run.f 9KB
run.f 831B
共 1081 条
- 1
- 2
- 3
- 4
- 5
- 6
- 11
chylinne
- 粉丝: 150
- 资源: 1
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论0