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###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 3.0
## \ \ Application : MIG
## / / Filename : readme.txt
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Steps to run simulations using Modelsim/QuestaSim,
## Cadence IES, and Synopsys VCS
## Assumptions : Simulations are run in \sim folder of MIG output "Open IP
## Example Design" directory
## Reference :
## Revision History:
###############################################################################
MIG outputs script files required to run the simulations for Modelsim/QuestaSim,
Vivado Simulator, IES and VCS. These scripts are valid only for running
simulations for "Open IP Example Design"
1. How to run simulations in Modelsim/QuestaSim simulator
A) sim.do File :
a) The 'sim.do' file has commands to compile and simulate memory
interface design and run the simulation for specified period of time.
b) It has the syntax to Map the required libraries (unisims_ver,
unisim and secureip). The libraries should be mapped using
the following command
vmap unisims_ver <unisims_ver lib path>
vmap unisim <unisim lib path>
vmap secureip <secureip lib path>
Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file
c) Displays the waveforms that are listed with "add wave" command.
B) Steps to run the Modelsim/QuestaSim simulation:
a) The user should invoke the Modelsim/QuestaSim simulator GUI.
b) Change the present working directory path to the sim folder.
In Transcript window, at Modelsim/QuestaSim prompt, type the following
command to change directory path.
cd <sim directory path>
c) Run the simulation using sim.do file.
At Modelsim/QuestaSim prompt, type the following command:
do sim.do
d) To exit simulation, type the following command at Modelsim/QuestaSim
prompt:
quit -f
e) Verify the transcript file for the memory transactions.
2. How to run simulations in Vivado simulator
A) Following files are provided :
a) The 'xsim_run.bat' is the executable file for Vivado simulator under
MicroSoft Windows environment.
b) The 'xsim_run.sh' is the executable file for Vivado simulator under
Linux environment.
c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and
simulate memory interface design and run the simulation for specified
period of time.
d) xsim_options.tcl file has commands to add waveforms and simulation
period.
e) xsim_files.prj file has list of rtl files for simulating the design.
f) $XILINX_VIVADO environment variable must be set in order to compile
glbl.v file
B) Steps to run the Vivado Simulator simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using xsim_run.sh file under Linux environment and
xsim_run.bat under MicroSoft Windows environment.
c) Verify the transcript file for the memory transactions.
3. How to run Cadence IES Simulations
A) ies_run.sh File :
a) The "ies_run.sh" file contains the commands for simulation of the
hdl files.
b) Libraries must be mapped before running simulations. Following
procedure must be followed to before running simulations
1. Create two files named cds.lib and hdl.var in this directory
2. Create a directory 'worklib' in same directory.
mkdir worklib
3. Add following lines in the cds.lib file to map Xilinx libraries
DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim
DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver
DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip
DEFINE worklib ./worklib
4. ATTENTION: In above lines replace the path for libraries as per your
compiled Xilinx libraries directory
5. ATTENTION: Add the lines in the same order given above
6. Please make sure you need to map all Xilinx libraries mentioned above
7. Save and close the cds.lib file
Also, $XILINX_VIVADO environment variable must be set in order to
compile glbl.v file and the above mentioned library files
B) Steps to run the IES simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using ies_run.sh file. Type the following command:
./ies_run.sh
c) Verify the ies_sim.log file for the memory transactions.
4. How to run Synopsys VCS Simulations
A) vcs_run.sh File :
a) The "vcs_run.sh" file contains the commands for simulation of hdl files.
b) Libraries must be mapped before running simulations. Following
procedu
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该资源为ddr3数据读写代码工程,由vivado2018.2编写。低版本的软件请参考附带的教程,自行配置ip核。开发板为ax7035,芯片为xc7a35tfgg484,ddr3芯片为16bit位宽,直接上板使用,其他芯片需更改相关输入输出管脚。module文件代码量少,适合初学者了解ddr3的读写操作。
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xilinx fpga ddr3数据读写工程 (941个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
top.v.bak 8KB
mem_burst.v.bak 6KB
mem_test.v.bak 3KB
xsim_run.bat 3KB
xsim_run.bat 3KB
compile.bat 463B
elaborate.bat 408B
simulate.bat 270B
runme.bat 268B
runme.bat 268B
runme.bat 268B
runme.bat 268B
top.bin 2.09MB
top.bit 2.09MB
hw_ila_data_1_7872_1536025680.btree 0B
hw_ila_data_1_4300_1535450915.btree 0B
hw_ila_data_1_6432_1535100827.btree 0B
data128x256.coe 6KB
data128x256.coe 6KB
data128x256.coe 6KB
data_h16x256.coe 2KB
data_h16x256.coe 2KB
xsim.dbg 1.31MB
xsim.dbg 58KB
xsim.dbg 25KB
xsim.dbg 2KB
top_routed.dcp 15.13MB
top_placed.dcp 13.24MB
top_opt.dcp 8.57MB
ila_0.dcp 2.5MB
ddr3.dcp 2.49MB
ddr3.dcp 2.16MB
ddr3.dcp 2.16MB
ila_0.dcp 1.21MB
top.dcp 105KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 12KB
clk_wiz_0.dcp 9KB
compile.do 8KB
compile.do 8KB
compile.do 7KB
compile.do 7KB
sim.do 6KB
sim.do 6KB
compile.do 761B
compile.do 737B
compile.do 696B
compile.do 686B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 301B
simulate.do 291B
simulate.do 291B
simulate.do 195B
simulate.do 185B
elaborate.do 183B
elaborate.do 173B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
xsimk.exe 9.92MB
run.f 7KB
run.f 7KB
run.f 494B
run.f 478B
usage_statistics_webtalk.html 37KB
usage_statistics_ext_xsim.html 3KB
usage_statistics_ext_labtool.html 3KB
hw_ila_data_1.ila 5KB
xil_txt.in 1KB
xil_txt.in 1KB
xil_upgrade.in 1KB
xil_upgrade.in 1KB
.xsim_webtallk.info 64B
.xsim_webtallk.info 59B
xsim.ini 21KB
xsim.ini 21KB
xsim.ini 58B
vivado_5724.backup.jou 8KB
vivado_5576.backup.jou 4KB
webtalk.jou 895B
webtalk_9692.backup.jou 895B
vivado_6080.backup.jou 804B
vivado_3564.backup.jou 803B
vivado.jou 775B
vivado_8904.backup.jou 773B
vivado.jou 773B
webtalk.jou 765B
vivado.jou 740B
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