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###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 2.3
## \ \ Application : MIG
## / / Filename : readme.txt
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Steps to run simulations using Modelsim/QuestaSim,
## Cadence IES, and Synopsys VCS
## Assumptions : Simulations are run in \sim folder of MIG output "Open IP
## Example Design" directory
## Reference :
## Revision History:
###############################################################################
MIG outputs script files required to run the simulations for Modelsim/QuestaSim,
Vivado Simulator, IES and VCS. These scripts are valid only for running
simulations for "Open IP Example Design"
1. How to run simulations in Modelsim/QuestaSim simulator
A) sim.do File :
a) The 'sim.do' file has commands to compile and simulate memory
interface design and run the simulation for specified period of time.
b) It has the syntax to Map the required libraries (unisims_ver,
unisim and secureip). The libraries should be mapped using
the following command
vmap unisims_ver <unisims_ver lib path>
vmap unisim <unisim lib path>
vmap secureip <secureip lib path>
Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file
c) Displays the waveforms that are listed with "add wave" command.
B) Steps to run the Modelsim/QuestaSim simulation:
a) The user should invoke the Modelsim/QuestaSim simulator GUI.
b) Change the present working directory path to the sim folder.
In Transcript window, at Modelsim/QuestaSim prompt, type the following
command to change directory path.
cd <sim directory path>
c) Run the simulation using sim.do file.
At Modelsim/QuestaSim prompt, type the following command:
do sim.do
d) To exit simulation, type the following command at Modelsim/QuestaSim
prompt:
quit -f
e) Verify the transcript file for the memory transactions.
2. How to run simulations in Vivado simulator
A) Following files are provided :
a) The 'xsim_run.bat' is the executable file for Vivado simulator under
MicroSoft Windows environment.
b) The 'xsim_run.sh' is the executable file for Vivado simulator under
Linux environment.
c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and
simulate memory interface design and run the simulation for specified
period of time.
d) xsim_options.tcl file has commands to add waveforms and simulation
period.
e) xsim_files.prj file has list of rtl files for simulating the design.
f) $XILINX_VIVADO environment variable must be set in order to compile
glbl.v file
B) Steps to run the Vivado Simulator simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using xsim_run.sh file under Linux environment and
xsim_run.bat under MicroSoft Windows environment.
c) Verify the transcript file for the memory transactions.
3. How to run Cadence IES Simulations
A) ies_run.sh File :
a) The "ies_run.sh" file contains the commands for simulation of the
hdl files.
b) Libraries must be mapped before running simulations. Following
procedure must be followed to before running simulations
1. Create two files named cds.lib and hdl.var in this directory
2. Create a directory 'worklib' in same directory.
mkdir worklib
3. Add following lines in the cds.lib file to map Xilinx libraries
DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim
DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver
DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip
DEFINE worklib ./worklib
4. ATTENTION: In above lines replace the path for libraries as per your
compiled Xilinx libraries directory
5. ATTENTION: Add the lines in the same order given above
6. Please make sure you need to map all Xilinx libraries mentioned above
7. Save and close the cds.lib file
Also, $XILINX_VIVADO environment variable must be set in order to
compile glbl.v file and the above mentioned library files
B) Steps to run the IES simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using ies_run.sh file. Type the following command:
./ies_run.sh
c) Verify the ies_sim.log file for the memory transactions.
4. How to run Synopsys VCS Simulations
A) vcs_run.sh File :
a) The "vcs_run.sh" file contains the commands for simulation of hdl files.
b) Libraries must be mapped before running simulations. Following
procedu
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FPGA(XILINX) DDR3 内存条 读写测试 仿真通过 (VIVADO 2015.2) (379个子文件)
xsim_run.bat 3KB
elaborate.bat 490B
compile.bat 288B
simulate.bat 285B
runme.bat 229B
runme.bat 229B
xsim.dbg 1.99MB
DDR3_ip.dcp 4.22MB
DDR3_ip.dcp 4.22MB
example_top.dcp 159KB
vivado_pid4136.debug 540B
sim.do 6KB
xsimk.exe 11.28MB
usage_statistics_ext_xsim.html 3KB
xil_txt.in 1KB
.xsim_webtallk.info 64B
vivado_11588.backup.jou 1KB
vivado_11752.backup.jou 1KB
vivado.jou 1KB
webtalk.jou 660B
webtalk_13840.backup.jou 659B
vivado.jou 633B
vivado_5028.backup.jou 625B
vivado_9508.backup.jou 608B
vivado_844.backup.jou 555B
vivado.jou 547B
vivado.jou 536B
ISEWrap.js 5KB
ISEWrap.js 5KB
rundef.js 1KB
rundef.js 1KB
vivado_11588.backup.log 182.52MB
vivado_11752.backup.log 131.03MB
vivado.log 36.17MB
simulate.log 13.73MB
runme.log 628KB
runme.log 50KB
vivado_5028.backup.log 44KB
vivado_9508.backup.log 22KB
compile.log 20KB
tcl.log 14KB
elaborate.log 8KB
vivado.log 2KB
webtalk.log 1KB
webtalk_13840.backup.log 1KB
vivado_844.backup.log 976B
xsimkernel.log 342B
xsimcrash.log 0B
DDR3_1.lpr 290B
xsim.mem 8.62MB
fsm_encoding.os 2KB
xil_txt.out 138B
vivado.pb 1.03MB
vivado.pb 41KB
xvlog.pb 29KB
xelab.pb 17KB
example_top_utilization_synth.pb 231B
DDR3_ip_utilization_synth.pb 231B
mig_a.prj 17KB
mig.prj 17KB
sim_tb_top_vlog.prj 14KB
xsim_files.prj 12KB
xsim.reloc 12.54MB
DDR3_ip_utilization_synth.rpt 10KB
example_top_utilization_synth.rpt 7KB
dupFiles.rpt 89B
dupFiles.rpt 89B
.vivado.begin.rst 188B
.vivado.begin.rst 187B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
elab.rtd 222KB
elab.rtd 207KB
xsim.rtti 630B
mig_7series_v2_3_ddr_phy_prbs_rdlvl.sdb 418KB
mig_7series_v2_3_ddr_phy_init.sdb 300KB
ddr3_model.sdb 273KB
mig_7series_v2_3_ddr_phy_rdlvl.sdb 203KB
mig_7series_v2_3_ddr_mc_phy.sdb 121KB
mig_7series_v2_3_ddr_phy_4lanes.sdb 114KB
mig_7series_v2_3_ddr_mc_phy_wrapper.sdb 108KB
mig_7series_v2_3_ddr_calib_top.sdb 103KB
mig_7series_v2_3_ddr_phy_wrcal.sdb 87KB
mig_7series_v2_3_ddr_phy_top.sdb 87KB
mig_7series_v2_3_ddr_phy_dqs_found_cal_hr.sdb 84KB
mig_7series_v2_3_ddr_phy_dqs_found_cal.sdb 84KB
mig_7series_v2_3_ddr_phy_wrlvl.sdb 71KB
mig_7series_v2_3_mem_intfc.sdb 51KB
mig_7series_v2_3_ddr_prbs_gen.sdb 49KB
mig_7series_v2_3_arb_select.sdb 48KB
mig_7series_v2_3_bank_state.sdb 47KB
mig_7series_v2_3_mc.sdb 46KB
mig_7series_v2_3_memc_ui_top_std.sdb 46KB
@d@d@r3_ip_mig.sdb 46KB
mig_7series_v2_3_bank_mach.sdb 39KB
mig_7series_v2_3_ddr_byte_lane.sdb 37KB
mig_7series_v2_3_ddr_phy_ocd_po_cntlr.sdb 31KB
mig_7series_v2_3_ddr_phy_ocd_lim.sdb 31KB
共 379 条
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资源评论
- lhhit12ji2018-05-15实例程序,xilinx公司有免费提供,没有参考价值
- kidletsh2019-04-26谢谢楼主分享
- crazyhertz0072019-05-16不错。。。
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