4位除法器位除法器vhdl程序程序
VHDL全名Very-High-Speed Integrated Circuit Hardware Description Language,诞生于1982年。1987年
底，VHDL被IEEE和美国国防部确认为标准硬件描述语言 。 VHDL和Verilog作为IEEE的工业标准硬件描述语
言，得到众多EDA公司支持，在电子工程领域，已成为事实上的通用硬件描述语言。
4位除法器,vhdl
--
--
--------------------------------------------------------------------------------/
-- DESCRIPTION : Signed pider
-- A (A) input width : 4
-- B (B) input width : 4
-- Q (data_out) output width : 4
-- DIV_BY_0 (DIVz) output active : high
-- Download from : http://www.pld.com.cn
--------------------------------------------------------------------------------/
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fpp is
port (
DIVz: out STD_LOGIC;
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
data_out: out STD_LOGIC_VECTOR (3 downto 0)
);
end fpp;
architecture fpp_arch of fpp is
signal REMAINDERS0 : STD_LOGIC_VECTOR (5 downto 0);
signal REMAINDERS1 : STD_LOGIC_VECTOR (5 downto 0);
signal REMAINDERS2 : STD_LOGIC_VECTOR (5 downto 0);
signal REMAINDERS3 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS0 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS1 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS2 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS3 : STD_LOGIC_VECTOR (5 downto 0);
signal Q_TEMP : STD_LOGIC_VECTOR (3 downto 0);
signal Z0 : STD_LOGIC_VECTOR (2 downto 0);
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