vhdl 程序实例
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2013-07-02
08:04:13
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1.动态扫描显示程序：
library ieee;
use ieee.std_logic_1164.all;
entity dtsm_xs is
port(clk:in std_logic;
B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1:in std_logic_vector(3 downto 0);
x:out std_logic_vector(6 downto 0);
led_select: out std_logic_vector(13 downto 0));
end;
architecture behave of dtsm_xs is
signal bcd_in: std_logic_vector(3 downto 0);
signal cnt2: integer range 0 to 13;
begin
p1:process(clk)
begin
if clk'event and clk='1' then
if cnt2>=13 then
cnt2<=0;
else
cnt2<=cnt2+1;
end if;
end if;
end process;
p2:process(cnt2,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1)
begin
case cnt2 is
when 0=>led_select<="11111111111110";bcd_in<=B1;
when 1=>led_select<="11111111111101";bcd_in<=B2;
when 2=>led_select<="11111111111011";bcd_in<=B3;
when 3=>led_select<="11111111110111";bcd_in<=B4;
when 4=>led_select<="11111111101111";bcd_in<=B5;
when 5=>led_select<="11111111011111";bcd_in<=B6;
when 6=>led_select<="11111110111111";bcd_in<=B7;
when 7=>led_select<="11111101111111";bcd_in<=B8;
when 8=>led_select<="11111011111111";bcd_in<=B9;
when 9=>led_select<="11110111111111";bcd_in<=B10;
when 10=>led_select<="11101111111111";bcd_in<=B11;
when 11=>led_select<="11011111111111";bcd_in<=B12;
when 12=>led_select<="10111111111111";bcd_in<=B13;
when 13=>led_select<="01111111111111";bcd_in<=B14;
end case;
end process;
p3:process(bcd_in)
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