READ Preamble .......................................................................................................................................... 63
READ Preamble Training ............................................................................................................................ 63
Temperature-Controlled Refresh ................................................................................................................. 63
Command Address Latency ........................................................................................................................ 63
Internal V
REF
Monitor ................................................................................................................................. 63
Maximum Power Savings Mode ................................................................................................................... 64
Mode Register 5 .............................................................................................................................................. 65
Data Bus Inversion ..................................................................................................................................... 66
Data Mask .................................................................................................................................................. 67
CA Parity Persistent Error Mode .................................................................................................................. 67
ODT Input Buffer for Power-Down .............................................................................................................. 67
CA Parity Error Status ................................................................................................................................. 67
CRC Error Status ......................................................................................................................................... 67
CA Parity Latency Mode .............................................................................................................................. 67
Mode Register 6 .............................................................................................................................................. 68
t
CCD_L Programming ................................................................................................................................. 69
V
REFDQ
Calibration Enable .......................................................................................................................... 69
V
REFDQ
Calibration Range ........................................................................................................................... 69
V
REFDQ
Calibration Value ............................................................................................................................ 70
Truth Tables ................................................................................................................................................... 71
NOP Command .............................................................................................................................................. 74
DESELECT Command .................................................................................................................................... 74
DLL-Off Mode ................................................................................................................................................ 74
DLL-On/Off Switching Procedures .................................................................................................................. 76
DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 76
DLL-Off to DLL-On Procedure .................................................................................................................... 78
Input Clock Frequency Change ....................................................................................................................... 79
Write Leveling ................................................................................................................................................ 80
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 81
Procedure Description ................................................................................................................................ 82
Write Leveling Mode Exit ............................................................................................................................ 83
Command Address Latency ............................................................................................................................ 85
Low-Power Auto Self Refresh Mode ................................................................................................................. 90
Manual Self Refresh Mode .......................................................................................................................... 90
Multipurpose Register .................................................................................................................................... 92
MPR Reads ................................................................................................................................................. 93
MPR Readout Format ................................................................................................................................. 95
MPR Readout Serial Format ........................................................................................................................ 95
MPR Readout Parallel Format ..................................................................................................................... 96
MPR Readout Staggered Format .................................................................................................................. 97
MPR READ Waveforms ............................................................................................................................... 98
MPR Writes ............................................................................................................................................... 100
MPR WRITE Waveforms ............................................................................................................................. 101
MPR REFRESH Waveforms ........................................................................................................................ 102
Gear-Down Mode .......................................................................................................................................... 105
Maximum Power-Saving Mode ....................................................................................................................... 108
Maximum Power-Saving Mode Entry .......................................................................................................... 108
Maximum Power-Saving Mode Entry in PDA .............................................................................................. 109
CKE Transition During Maximum Power-Saving Mode ................................................................................ 109
Maximum Power-Saving Mode Exit ............................................................................................................ 109
Command/Address Parity .............................................................................................................................. 111
Per-DRAM Addressability .............................................................................................................................. 119
8Gb: x4, x8, x16 DDR4 SDRAM
Features
CCMTD-1725822587-9875
8gb_ddr4_dram.pdf - Rev. P 04/19 EN
5
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