PCI-to-PCI Bridge Architecture
Specification
Revision 1.1
December 18, 1998
Revision 1.1
22
Revision History
Revision Issue Date Comments
1.0 4/5/94 Original issue
1.1 12/18/98 Update to include target initial latency requirements.
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Revision 1.1
3
CONTENTS
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1.1. Goals and Non-Goals of this Specification.......................................................................................................11
1.2. Overview and Terminology...............................................................................................................................11
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2.1. Summary of Key Requirements........................................................................................................................15
2.2. Capabilities Not Supported...............................................................................................................................16
2.3. Optional Capabilities.........................................................................................................................................17
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3.1. Overview of Hierarchical Configuration..........................................................................................................19
3.1.1. Type 0 Configuration Transaction Support...................................................................................................20
3.1.2. Type 1 Configuration Transaction Support...................................................................................................20
3.1.2.1. Primary Interface...................................................................................................................................20
3.1.2.1.1. Type 1 to Type 0 Conversion.........................................................................................................21
3.1.2.1.2. Type 1 to Type 1 Forwarding.........................................................................................................23
3.1.2.1.3. Type 1 to Special Cycle Conversion..............................................................................................23
3.1.2.2. Secondary Interface...............................................................................................................................23
3.1.2.2.1. Type 1 to Type 1 Forwarding.........................................................................................................24
3.1.2.2.2. Type 1 to Special Cycle Conversion..............................................................................................24
3.2. PCI-to-PCI Bridge Configuration Space Header Format ..............................................................................25
3.2.1. Access of Reserved Registers.......................................................................................................................26
3.2.2. Access of Reserved Bit Fields ......................................................................................................................26
3.2.3. Reset Events .................................................................................................................................................26
3.2.4. Common Format Configuration Registers....................................................................................................26
3.2.4.1. Vendor ID Register................................................................................................................................26
3.2.4.2. Device ID Register................................................................................................................................26
3.2.4.3. Command Register................................................................................................................................27
3.2.4.4. Status Register.......................................................................................................................................31
3.2.4.5. Revision ID Register .............................................................................................................................34
3.2.4.6. Class Code Register...............................................................................................................................34
3.2.4.7. Cacheline Size Register.........................................................................................................................35
3.2.4.8. Latency Timer Register.........................................................................................................................36
3.2.4.9. Header Type Register............................................................................................................................36
3.2.4.10. BIST Register......................................................................................................................................36
3.2.5. Bridge Specific Configuration Registers.......................................................................................................37
3.2.5.1. Base Address Registers .........................................................................................................................37
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3.2.5.1.1. Memory Base Address Register Format.........................................................................................38
3.2.5.1.2. I/O Base Address Register Format.................................................................................................39
3.2.5.2. Primary Bus Number Register...............................................................................................................40
3.2.5.3. Secondary Bus Number Register...........................................................................................................40
3.2.5.4. Subordinate Bus Number Register ........................................................................................................40
3.2.5.5. Secondary Latency Timer Register .......................................................................................................40
3.2.5.6. I/O Base Register and I/O Limit Register..............................................................................................41
3.2.5.7. Secondary Status Register.....................................................................................................................42
3.2.5.8. Memory Base Register and Memory Limit Register.............................................................................45
3.2.5.9. Prefetchable Memory Base Register and Prefetchable Memory Limit Register ...................................46
3.2.5.10. Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits Registers.............................46
3.2.5.11. I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits Registers..........................................................47
3.2.5.12. Capabilities Pointer..............................................................................................................................47
3.2.5.13. Reserved Registers at 35h, 36h, and 37h.............................................................................................47
3.2.5.14. Expansion ROM Base Address Register .............................................................................................48
3.2.5.15. Interrupt Line Register.........................................................................................................................48
3.2.5.16. Interrupt Pin Register...........................................................................................................................48
3.2.5.17. Bridge Control Register.......................................................................................................................49
3.2.6. Slot Numbering Capabilities List Item .........................................................................................................55
3.2.6.1. Slot Numbering Capabilities ID ............................................................................................................55
3.2.6.2. Pointer to Next ID .................................................................................................................................55
3.2.6.3. Expansion Slot Register.........................................................................................................................55
3.2.6.4. Chassis Number Register.......................................................................................................................56
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4.1. Address Ranges..................................................................................................................................................57
4.2. I/O........................................................................................................................................................................57
4.2.1. ISA Mode .....................................................................................................................................................59
4.3. Memory Mapped I/O.........................................................................................................................................60
4.4. Prefetchable Memory.........................................................................................................................................62
4.4.1. 64-bit Addressing..........................................................................................................................................63
4.4.2. 64-bit Address Decoding of Prefetchable Memory.......................................................................................65
4.4.2.1. Below the 4 GB Boundary.....................................................................................................................66
4.4.2.2. Above the 4 GB Boundary ....................................................................................................................66
4.4.2.3. Across the 4 GB Boundary....................................................................................................................66
4.5. VGA Support......................................................................................................................................................67
4.5.1. VGA Compatible Addressing.......................................................................................................................67
4.5.2. VGA Palette Snooping..................................................................................................................................67
4.6. Subtractive Decode Support..............................................................................................................................68
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5.1. Prefetching Read Data.......................................................................................................................................69
5.2. Posting Write Data.............................................................................................................................................71
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5.2.1. Memory Write and Invalidate Usage............................................................................................................71
5.2.1.1. Forwarding Memory Write and Invalidate Transactions........................................................................71
5.2.1.2. Promoting Memory Write Transactions ................................................................................................72
5.2.1.3. Combining Memory Write Transactions...............................................................................................72
5.2.1.4. Memory Write and Invalidate Disconnects ............................................................................................73
5.2.1.4.1. Master Disconnected by the Bridge ...............................................................................................73
5.2.1.4.2. Bridge Disconnected by the Target................................................................................................73
5.3. Delayed Transactions.........................................................................................................................................74
5.3.1. Discarding a Delayed Request.......................................................................................................................75
5.3.2. Discarding a Delayed Completion.................................................................................................................76
5.4. Exclusive Access Transactions..........................................................................................................................76
5.4.1. Delayed Lock-Request Error ........................................................................................................................77
5.4.2. Normal Completion ......................................................................................................................................77
5.5. Ordering Requirements.....................................................................................................................................78
5.6. Special Design Considerations ..........................................................................................................................88
5.6.1. Read Starvation.............................................................................................................................................88
5.6.2. Stale Data......................................................................................................................................................89
5.6.3. Deadlocks .....................................................................................................................................................89
5.7. Combining Separate Writes Into a Single Burst Transaction........................................................................91
5.8. Merging Separate Writes Into a Single Transaction.......................................................................................91
5.9. Collapsing of Writes...........................................................................................................................................91
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6.1. Introduction........................................................................................................................................................93
6.2. Parity Errors ......................................................................................................................................................95
6.2.1. Address Parity Errors....................................................................................................................................95
6.2.2. Read Data Parity Errors................................................................................................................................96
6.2.2.1. Target Completion Error .......................................................................................................................96
6.2.2.2. Master Completion Error.......................................................................................................................97
6.2.3. Non-Posted Write Data Parity Errors............................................................................................................97
6.2.3.1. Master Request Error.............................................................................................................................98
6.2.3.2. Target Completion Error .......................................................................................................................98
6.2.3.3. Master Completion Error.......................................................................................................................99
6.2.4. Posted Write Data Parity Errors..................................................................................................................100
6.2.4.1. Originating Bus Error..........................................................................................................................100
6.2.4.2. Destination Bus Error..........................................................................................................................101
6.3. Master-Aborts ..................................................................................................................................................101
6.3.1. Non-posted Transactions ............................................................................................................................101
6.3.2. Posted Write Transactions ..........................................................................................................................102
6.3.3. Exclusive Access Master-Abort..................................................................................................................103
