Revision 1.1
4
3.2.5.1.1. Memory Base Address Register Format.........................................................................................38
3.2.5.1.2. I/O Base Address Register Format.................................................................................................39
3.2.5.2. Primary Bus Number Register...............................................................................................................40
3.2.5.3. Secondary Bus Number Register...........................................................................................................40
3.2.5.4. Subordinate Bus Number Register ........................................................................................................40
3.2.5.5. Secondary Latency Timer Register .......................................................................................................40
3.2.5.6. I/O Base Register and I/O Limit Register..............................................................................................41
3.2.5.7. Secondary Status Register.....................................................................................................................42
3.2.5.8. Memory Base Register and Memory Limit Register.............................................................................45
3.2.5.9. Prefetchable Memory Base Register and Prefetchable Memory Limit Register ...................................46
3.2.5.10. Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits Registers.............................46
3.2.5.11. I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits Registers..........................................................47
3.2.5.12. Capabilities Pointer..............................................................................................................................47
3.2.5.13. Reserved Registers at 35h, 36h, and 37h.............................................................................................47
3.2.5.14. Expansion ROM Base Address Register .............................................................................................48
3.2.5.15. Interrupt Line Register.........................................................................................................................48
3.2.5.16. Interrupt Pin Register...........................................................................................................................48
3.2.5.17. Bridge Control Register.......................................................................................................................49
3.2.6. Slot Numbering Capabilities List Item .........................................................................................................55
3.2.6.1. Slot Numbering Capabilities ID ............................................................................................................55
3.2.6.2. Pointer to Next ID .................................................................................................................................55
3.2.6.3. Expansion Slot Register.........................................................................................................................55
3.2.6.4. Chassis Number Register.......................................................................................................................56
&+$37(5$''5(66'(&2',1*
4.1. Address Ranges..................................................................................................................................................57
4.2. I/O........................................................................................................................................................................57
4.2.1. ISA Mode .....................................................................................................................................................59
4.3. Memory Mapped I/O.........................................................................................................................................60
4.4. Prefetchable Memory.........................................................................................................................................62
4.4.1. 64-bit Addressing..........................................................................................................................................63
4.4.2. 64-bit Address Decoding of Prefetchable Memory.......................................................................................65
4.4.2.1. Below the 4 GB Boundary.....................................................................................................................66
4.4.2.2. Above the 4 GB Boundary ....................................................................................................................66
4.4.2.3. Across the 4 GB Boundary....................................................................................................................66
4.5. VGA Support......................................................................................................................................................67
4.5.1. VGA Compatible Addressing.......................................................................................................................67
4.5.2. VGA Palette Snooping..................................................................................................................................67
4.6. Subtractive Decode Support..............................................................................................................................68
&+$37(5%8))(50$1$*(0(17
5.1. Prefetching Read Data.......................................................................................................................................69
5.2. Posting Write Data.............................................................................................................................................71
jitao_xa2015-06-05正在研究PCI，参考一下。
