新鲜出炉的PCI-E协议3.0

Contents OBJECTIVE OF THE SPECIFICATION............................................................................... 23 DOCUMENT ORGANIZATION.............................................................................................. 23 DOCUMENTATION CONVENTIONS................................................................................... 24 TERMS AND ACRONYMS ...................................................................................................... 25 REFERENCE DOCUMENTS................................................................................................... 32 1. INTRODUCTION............................................................................................................... 33 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 33 1.2. PCI EXPRESS LINK......................................................................................................... 35 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 37 1.3.1. Root Complex........................................................................................................ 37 1.3.2. Endpoints .............................................................................................................. 38 1.3.3. Switch.................................................................................................................... 41 1.3.4. Root Complex Event Collector.............................................................................. 42 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 42 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 42 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 43 1.5.1. Transaction Layer................................................................................................. 44 1.5.2. Data Link Layer .................................................................................................... 44 1.5.3. Physical Layer ...................................................................................................... 45 1.5.4. Layer Functions and Services............................................................................... 45 2. TRANSACTION LAYER SPECIFICATION ................................................................. 49 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 49 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 50 2.1.2. Packet Format Overview ...................................................................................... 52 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 53 2.2.1. Common Packet Header Fields ............................................................................ 53 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 56 2.2.3. TLP Digest Rules .................................................................................................. 60 2.2.4. Routing and Addressing Rules.............................................................................. 60 2.2.5. First/Last DW Byte Enables Rules........................................................................ 64 2.2.6. Transaction Descriptor......................................................................................... 67 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 72 2.2.8. Message Request Rules......................................................................................... 77 2.2.9. Completion Rules.................................................................................................. 91 2.3. HANDLING OF RECEIVED TLPS...................................................................................... 94 2.3.1. Request Handling Rules........................................................................................ 97 2.3.2. Completion Handling Rules................................................................................ 110 2.4. TRANSACTION ORDERING ............................................................................................ 112 2.4.1. Transaction Ordering Rules ............................................................................... 112 2.4.2. Update Ordering and Granularity Observed by a Read Transaction ................ 118 2.4.3. Update Ordering and Granularity Provided by a Write Transaction ................ 119 2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 119 2.5.1. Virtual Channel Identification (VC ID) .............................................................. 121 2.5.2. TC to VC Mapping.............................................................................................. 122 2.5.3. VC and TC Rules................................................................................................. 123 2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 124 2.6.1. Flow Control Rules............................................................................................. 125 2.7. DATA INTEGRITY ......................................................................................................... 135 2.7.1. ECRC Rules ........................................................................................................ 136 2.7.2. Error Forwarding ............................................................................................... 140 2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 142 2.9. LINK STATUS DEPENDENCIES ...................................................................................... 143 2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 143 2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 144 3. DATA LINK LAYER SPECIFICATION ...................................................................... 145 3.1. DATA LINK LAYER OVERVIEW .................................................................................... 145 3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 147 3.2.1. Data Link Control and Management State Machine Rules ................................ 148 3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 150 3.3.1. Flow Control Initialization State Machine Rules ............................................... 150 3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 154 3.4.1. Data Link Layer Packet Rules ............................................................................ 154 3.5. DATA INTEGRITY ......................................................................................................... 159 3.5.1. Introduction......................................................................................................... 159 3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 159 3.5.3. LCRC and Sequence Number (TLP Receiver) .................................................... 171 4. PHYSICAL LAYER SPECIFICATION ........................................................................ 179 4.1. INTRODUCTION ............................................................................................................ 179 4.2. LOGICAL SUB-BLOCK................................................................................................... 179 4.2.1. Encoding for 2.5 GT/s and 5 GT/s Data Rates ................................................... 180 4.2.2. Encoding for 8GT/s and Higher Data Rates....................................................... 188 4.2.3. <Placeholder>.................................................................................................... 204 4.2.4. Link Initialization and Training.......................................................................... 204 4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 219 4.2.6. Link Training and Status State Rules.................................................................. 222 4.2.7. Clock Tolerance Compensation.......................................................................... 269 4.2.8. Compliance Pattern ............................................................................................ 272 4.2.9. Modified Compliance Pattern............................................................................. 273 4.3. ELECTRICAL SUB-BLOCK ............................................................................................. 275 4.3.1. Maintaining Backwards Compatibility............................................................... 275 4.3.2. Jitter Budgeting and Measurement..................................................................... 277 4.3.3. Transmitter Specification.................................................................................... 278 4.3.4. Receiver Specification......................................................................................... 293 4.3.5. Transmitter and Receiver DC Specifications...................................................... 307 4.3.6. Channel Specifications........................................................................................ 312 4.3.7. Reference Clock Specifications........................................................................... 319 4.4. 8.0G ELECTRICAL SPECIFICATION ............................................................................... 327 4.4.1. 8.0G Transmitter Specifications ......................................................................... 327 4.4.2. 8.0G Receiver Specifications .............................................................................. 335 4.4.3. Channel Compliance Testing.............................................................................. 345 4.4.4. Refclk Parameters for 8.0G ................................................................................ 352 5. POWER MANAGEMENT .............................................................................................. 357 5.1. OVERVIEW ................................................................................................................... 357 5.1.1. Statement of Requirements.................................................................................. 358 5.2. LINK STATE POWER MANAGEMENT............................................................................. 358 5.3. PCI-PM SOFTWARE COMPATIBLE MECHANISMS......................................................... 363 5.3.1. Device Power Management States (D-States) of a Function.............................. 363 5.3.2. PM Software Control of the Link Power Management State.............................. 367 5.3.3. Power Management Event Mechanisms ............................................................. 373 5.4. NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS ....................................... 380 5.4.1. Active State Power Management (ASPM) .......................................................... 380 5.5. AUXILIARY POWER SUPPORT....................................................................................... 396 5.5.1. Auxiliary Power Enabling................................................................................... 396 5.6. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 397 6. SYSTEM ARCHITECTURE .......................................................................................... 399 6.1. INTERRUPT AND PME SUPPORT ................................................................................... 399 6.1.1. Rationale for PCI Express Interrupt Model........................................................ 399 6.1.2. PCI Compatible INTx Emulation........................................................................ 400 6.1.3. INTx Emulation Software Model ........................................................................ 400 6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 400 6.1.5. PME Support....................................................................................................... 402 6.1.6. Native PME Software Model .............................................................................. 402 6.1.7. Legacy PME Software Model ............................................................................. 403 6.1.8. Operating System Power Management Notification........................................... 403 6.1.9. PME Routing Between PCI Express and PCI Hierarchies ................................ 403 6.2. ERROR SIGNALING AND LOGGING................................................................................ 404 6.2.1. Scope................................................................................................................... 404 6.2.2. Error Classification ............................................................................................ 404 6.2.3. Error Signaling ................................................................................................... 406 6.2.4. Error Logging ..................................................................................................... 413 6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 417 6.2.6. Error Message Controls ..................................................................................... 420 6.2.7. Error Listing and Rules ...................................................................................... 421 6.2.8. Virtual PCI Bridge Error Handling.................................................................... 426 6.2.9. Internal Errors.................................................................................................... 427 6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 428 6.3.1. Introduction and Scope....................................................................................... 428 6.3.2. TC/VC Mapping and Example Usage................................................................. 429 6.3.3. VC Arbitration .................................................................................................... 431 6.3.4. Isochronous Support ........................................................................................... 439 6.4. DEVICE SYNCHRONIZATION......................................................................................... 442 6.5. LOCKED TRANSACTIONS.............................................................................................. 443 6.5.1. Introduction......................................................................................................... 443 6.5.2. Initiation and Propagation of Locked Transactions - Rules............................... 444 6.5.3. Switches and Lock - Rules................................................................................... 445 6.5.4. PCI Express/PCI Bridges and Lock - Rules ....................................................... 445 6.5.5. Root Complex and Lock - Rules.......................................................................... 446 6.5.6. Legacy Endpoints................................................................................................ 446 6.5.7. PCI Express Endpoints ....................................................................................... 446 6.6. PCI EXPRESS RESET - RULES ....................................................................................... 446 6.6.1. Conventional Reset ............................................................................................. 446 6.6.2. Function-Level Reset (FLR)................................................................................ 449 6.7. PCI EXPRESS HOT-PLUG SUPPORT .............................................................................. 452 6.7.1. Elements of Hot-Plug.......................................................................................... 453 6.7.2. Registers Grouped by Hot-Plug Element Association........................................ 459 6.7.3. PCI Express Hot-Plug Events............................................................................. 461 6.7.4. Firmware Support for Hot-Plug ......................................................................... 464 6.8. POWER BUDGETING CAPABILITY ................................................................................. 464 6.8.1. System Power Budgeting Process Recommendations......................................... 465 6.9. SLOT POWER LIMIT CONTROL ..................................................................................... 465 6.10. ROOT COMPLEX TOPOLOGY DISCOVERY ................................................................. 468 6.11. LINK SPEED MANAGEMENT ..................................................................................... 470 6.12. ACCESS CONTROL SERVICES (ACS) ........................................................................ 471 6.12.1. ACS Component Capability Requirements ......................................................... 472 6.12.2. Interoperability ................................................................................................... 476 6.12.3. ACS Peer-to-Peer Control Interactions.............................................................. 477 6.12.4. ACS Violation Error Handling ........................................................................... 477 6.12.5. ACS Redirection Impacts on Ordering Rules ..................................................... 478 6.13. ALTERNATIVE ROUTING-ID INTERPRETATION (ARI) .............................................. 480 6.14. MULTICAST OPERATIONS......................................................................................... 485 6.14.1. Multicast TLP Processing................................................................................... 485 6.14.2. Multicast Ordering.............................................................................................. 487 6.14.3. Multicast Capability Structure Field Updates.................................................... 488 6.14.4. MC Blocked TLP Processing.............................................................................. 488 6.14.5. MC_Overlay Mechanism .................................................................................... 488 6.15. ATOMIC OPERATIONS (ATOMICOPS) ....................................................................... 492 6.15.1. AtomicOp Use Models and Benefits ................................................................... 493 6.15.2. AtomicOp Transaction Protocol Summary......................................................... 493 6.15.3. Root Complex Support for AtomicOps................................................................ 495 6.16. DYNAMIC POWER ALLOCATION (DPA) CAPABILITY ............................................... 497 6.16.1. DPA Capability with Multi-Function Devices.................................................... 498 6.17. TLP PROCESSING HINT............................................................................................ 499 6.17.1. Processing Hint................................................................................................... 499 6.17.2. Steering Tag Table.............................................................................................. 500 6.17.3. ST Mode .............................................................................................................. 500 6.17.4. TPH Capability ................................................................................................... 501 6.18. LATENCY TOLERANCE REPORTING (LTR) MECHANISM .......................................... 502 6.19. OPPORTUNISTIC BUFFER FLUSH/FILL (OBFF) MECHANISM .................................... 507 6.20. TLP PREFIX ............................................................................................................. 510 7. SOFTWARE INITIALIZATION AND CONFIGURATION...................................... 511 7.1. CONFIGURATION TOPOLOGY........................................................................................ 511 7.2. PCI EXPRESS CONFIGURATION MECHANISMS ............................................................. 512 7.2.1. PCI 3.0 Compatible Configuration Mechanism ................................................. 513 7.2.2. PCI Express Enhanced Configuration Access Mechanism (ECAM).................. 514 7.2.3. Root Complex Register Block ............................................................................. 518 7.3. CONFIGURATION TRANSACTION RULES ....................................................................... 519 7.3.1. Device Number.................................................................................................... 519 7.3.2. Configuration Transaction Addressing............................................................... 520 7.3.3. Configuration Request Routing Rules................................................................. 520 7.3.4. PCI Special Cycles.............................................................................................. 521 7.4. CONFIGURATION REGISTER TYPES .............................................................................. 522 7.5. PCI-COMPATIBLE CONFIGURATION REGISTERS........................................................... 523 7.5.1. Type 0/1 Common Configuration Space............................................................. 524 7.5.2. Type 0 Configuration Space Header................................................................... 530 7.5.3. Type 1 Configuration Space Header................................................................... 532 7.6. PCI POWER MANAGEMENT CAPABILITY STRUCTURE.................................................. 536 7.7. MSI AND MSI-X CAPABILITY STRUCTURES ................................................................ 537 7.8. PCI EXPRESS CAPABILITY STRUCTURE........................................................................ 538 7.8.1. PCI Express Capability List Register (Offset 00h)............................................. 539 7.8.2. PCI Express Capabilities Register (Offset 02h) ................................................. 540 7.8.3. Device Capabilities Register (Offset 04h) .......................................................... 542 7.8.4. Device Control Register (Offset 08h) ................................................................. 547 7.8.5. Device Status Register (Offset 0Ah).................................................................... 553 7.8.6. Link Capabilities Register (Offset 0Ch).............................................................. 556 7.8.7. Link Control Register (Offset 10h) ..................................................................... 560 7.8.8. Link Status Register (Offset 12h) ........................................................................ 568 7.8.9. Slot Capabilities Register (Offset 14h) ............................................................... 571 7.8.10. Slot Control Register (Offset 18h) ...................................................................... 573 7.8.11. Slot Status Register (Offset 1Ah)......................................................................... 577 7.8.12. Root Control Register (Offset 1Ch) .................................................................... 579 7.8.13. Root Capabilities Register (Offset 1Eh) ............................................................. 581 7.8.14. Root Status Register (Offset 20h)........................................................................ 581 7.8.15. Device Capabilities 2 Register (Offset 24h) ....................................................... 583 7.8.16. Device Control 2 Register (Offset 28h) .............................................................. 587 7.8.17. Device Status 2 Register (Offset 2Ah)................................................................. 590 7.8.18. Link Capabilities 2 Register (Offset 2Ch)........................................................... 590 7.8.19. Link Control 2 Register (Offset 30h) .................................................................. 590 7.8.20. Link Status 2 Register (Offset 32h) ..................................................................... 595 7.8.21. Slot Capabilities 2 Register (Offset 34h) ............................................................ 595 7.8.22. Slot Control 2 Register (Offset 38h) ................................................................... 595 7.8.23. Slot Status 2 Register (Offset 3Ah)...................................................................... 595 7.9. PCI EXPRESS EXTENDED CAPABILITIES....................................................................... 596 7.9.1. Extended Capabilities in Configuration Space................................................... 596 7.9.2. Extended Capabilities in the Root Complex Register Block............................... 596 7.9.3. PCI Express Extended Capability Header.......................................................... 597 7.10. ADVANCED ERROR REPORTING CAPABILITY ........................................................... 598 7.10.1. Advanced Error Reporting Extended Capability Header (Offset 00h)............... 599 7.10.2. Uncorrectable Error Status Register (Offset 04h).............................................. 600 7.10.3. Uncorrectable Error Mask Register (Offset 08h)............................................... 601 7.10.4. Uncorrectable Error Severity Register (Offset 0Ch).......................................... 603 7.10.5. Correctable Error Status Register (Offset 10h).................................................. 606 7.10.6. Correctable Error Mask Register (Offset 14h)................................................... 608 7.10.7. Advanced Error Capabilities and Control Register (Offset 18h) ....................... 609 7.10.8. Header Log Register (Offset 1Ch) ...................................................................... 611 7.10.9. Root Error Command Register (Offset 2Ch) ...................................................... 612 7.10.10. Root Error Status Register (Offset 30h).......................................................... 613 7.10.11. Error Source Identification Register (Offset 34h) .......................................... 616 7.11. VIRTUAL CHANNEL CAPABILITY ............................................................................. 617 7.11.1. Virtual Channel Extended Capability Header.................................................... 619 7.11.2. Port VC Capability Register 1 ............................................................................ 620 7.11.3. Port VC Capability Register 2 ............................................................................ 621 7.11.4. Port VC Control Register.................................................................................... 622 7.11.5. Port VC Status Register ...................................................................................... 623 7.11.6. VC Resource Capability Register ....................................................................... 624 7.11.7. VC Resource Control Register............................................................................ 626 7.11.8. VC Resource Status Register .............................................................................. 628 7.11.9. VC Arbitration Table .......................................................................................... 629 7.11.10. Port Arbitration Table .................................................................................... 630 7.12. DEVICE SERIAL NUMBER CAPABILITY..................................................................... 632 7.12.1. Device Serial Number Extended Capability Header (Offset 00h) ...................... 633 7.12.2. Serial Number Register (Offset 04h)................................................................... 634 7.13. PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ............................ 634 7.13.1. Root Complex Link Declaration Extended Capability Header........................... 636 7.13.2. Element Self Description..................................................................................... 637 7.13.3. Link Entries......................................................................................................... 638 7.14. PCI EXPRESS ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY................... 642 7.14.1. Root Complex Internal Link Control Extended Capability Header.................... 642 7.14.2. Root Complex Link Capabilities Register........................................................... 643 7.14.3. Root Complex Link Control Register.................................................................. 645 7.14.4. Root Complex Link Status Register..................................................................... 647 7.15. POWER BUDGETING CAPABILITY ............................................................................. 648 7.15.1. Power Budgeting Extended Capability Header (Offset 00h).............................. 648 7.15.2. Data Select Register (Offset 04h) ....................................................................... 649 7.15.3. Data Register (Offset 08h).................................................................................. 649 7.15.4. Power Budget Capability Register (Offset 0Ch)................................................. 652 7.16. ACS EXTENDED CAPABILITY .................................................................................. 652 7.16.1. ACS Extended Capability Header (Offset 00h) .................................................. 653 7.16.2. ACS Capability Register (Offset 04h)................................................................. 653 7.16.3. ACS Control Register (Offset 06h) ..................................................................... 655 7.16.4. Egress Control Vector (Offset 08h) .................................................................... 656 7.17. PCI EXPRESS ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY ............................................................................................................................. 658 7.17.1. Root Complex Event Collector Endpoint Association Extended Capability Header 658 7.17.2. Association Bitmap for Root Complex Integrated Endpoints............................. 659 7.18. MULTI-FUNCTION VIRTUAL CHANNEL CAPABILITY ................................................ 660 7.18.1. MFVC Extended Capability Header................................................................... 661 7.18.2. Port VC Capability Register 1 ............................................................................ 661 7.18.3. Port VC Capability Register 2 ............................................................................ 664 7.18.4. Port VC Control Register.................................................................................... 665 7.18.5. Port VC Status Register ...................................................................................... 666 7.18.6. VC Resource Capability Register ....................................................................... 666 7.18.7. VC Resource Control Register............................................................................ 668 7.18.8. VC Resource Status Register .............................................................................. 670 7.18.9. VC Arbitration Table .......................................................................................... 671 7.18.10. Function Arbitration Table............................................................................. 671 7.19. VENDOR-SPECIFIC CAPABILITY ............................................................................... 673 7.19.1. Vendor-Specific Extended Capability Header (Offset 00h)................................ 674 7.19.2. Vendor-Specific Header (Offset 04h).................................................................. 676 7.20. RCRB HEADER CAPABILITY ................................................................................... 677 7.20.1. RCRB Header Extended Capability Header (Offset 00h)................................... 677 7.20.2. Vendor ID (Offset 04h) and Device ID (Offset 06h)........................................... 678 7.20.3. RCRB Capabilities (Offset 08h).......................................................................... 679 7.20.4. RCRB Control (Offset 0Ch) ................................................................................ 679 7.21. MULTICAST CAPABILITY ......................................................................................... 680 7.21.1. Multicast Extended Capability Header (Offset 00h) .......................................... 681 7.21.2. Multicast Capability Register (Offset 04h)......................................................... 682 7.21.3. Multicast Control Register (Offset 06h) ............................................................. 683 7.21.4. Multicast Base Address Register (Offset 08h) .................................................... 684 7.21.5. MC_Receive Register (Offset 10h)...................................................................... 685 7.21.6. MC_Block_All Register (Offset 18h) .................................................................. 685 7.21.7. MC_Block_Untranslated Register (Offset 20h).................................................. 686 7.21.8. MC_Overlay_BAR (Offset 28h) .......................................................................... 687 7.22. RESIZABLE BAR CAPABILITY.................................................................................. 688 7.22.1. Resizable BAR Extended Capability Header (Offset 00h).................................. 689 7.22.2. Resizable BAR Capability Register (Offset 04h) ................................................ 690 7.22.3. Resizable BAR Control Register (Offset 08h)..................................................... 692 7.23. ARI CAPABILITY ..................................................................................................... 694 7.23.1. ARI Capability Header (Offset 00h) ................................................................... 694 7.23.2. ARI Capability Register (Offset 04h).................................................................. 695 7.23.3. ARI Control Register (Offset 06h) ...................................................................... 696 7.24. DYNAMIC POWER ALLOCATION (DPA) CAPABILITY ............................................... 697 7.24.1. DPA Extended Capability Header (Offset 00h).................................................. 698 7.24.2. DPA Capability Register (Offset 04h) ................................................................ 699 7.24.3. DPA Latency Indicator Register (Offset 08h)..................................................... 700 7.24.4. DPA Status Register (Offset 0Ch)....................................................................... 700 7.24.5. DPA Control Register (Offset 0Eh) .................................................................... 701 7.24.6. DPA Power Allocation Array ............................................................................. 701 7.25. LATENCY TOLERANCE REPORTING (LTR) CAPABILITY........................................... 702 7.25.1. LTR Extended Capability Header (Offset 00h)................................................... 702 7.25.2. Max Snoop Latency Register (Offset 04h) .......................................................... 703 7.25.3. Max No-Snoop Latency Register (Offset 06h) .................................................... 704 A. ISOCHRONOUS APPLICATIONS................................................................................... 705 A.1. INTRODUCTION ............................................................................................................ 705 A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ........................................... 707 A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot............................. 708 A.2.2. Isochronous Payload Size................................................................................... 709 A.2.3. Isochronous Bandwidth Allocation..................................................................... 709 A.2.4. Isochronous Transaction Latency....................................................................... 710 A.2.5. An Example Illustrating Isochronous Parameters.............................................. 711 A.3. ISOCHRONOUS TRANSACTION RULES........................................................................... 712 A.4. TRANSACTION ORDERING ............................................................................................ 712 A.5. ISOCHRONOUS DATA COHERENCY............................................................................... 712 A.6. FLOW CONTROL........................................................................................................... 713 A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ....................................................... 713 A.7.1. Isochronous Bandwidth of PCI Express Links.................................................... 713 A.7.2. Isochronous Bandwidth of Endpoints ................................................................. 713 A.7.3. Isochronous Bandwidth of Switches ................................................................... 713 A.7.4. Isochronous Bandwidth of Root Complex........................................................... 714 A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS ..................................................... 714 A.8.1. An Endpoint as a Requester................................................................................ 714 A.8.2. An Endpoint as a Completer............................................................................... 714 A.8.3. Switches............................................................................................................... 715 A.8.4. Root Complex...................................................................................................... 716 B. SYMBOL ENCODING ...................................................................................................... 717 C. PHYSICAL LAYER APPENDIX...................................................................................... 727 C.1. DATA SCRAMBLING ..................................................................................................... 727 D. REQUEST DEPENDENCIES............................................................................................ 733 E. ID-BASED ORDERING USAGE...................................................................................... 737 E.1. INTRODUCTION ............................................................................................................ 737 E.2. POTENTIAL BENEFITS WITH IDO USE .......................................................................... 738 E.2.1. Benefits for MFD/RP Direct Connect................................................................. 738 E.2.2. Benefits for Switched Environments ................................................................... 738 E.2.3. Benefits for Integrated Endpoints ....................................................................... 739 E.2.4. IDO Use in Conjunction with RO ....................................................................... 739 E.3. WHEN TO USE IDO...................................................................................................... 739 E.4. WHEN NOT TO USE IDO .............................................................................................. 740 E.4.1. When Not to Use IDO with Endpoints ................................................................ 740 E.4.2. When Not to Use IDO with Root Ports ............................................................... 740 E.5. SOFTWARE CONTROL OF IDO USE............................................................................... 741 E.5.1. Software Control of Endpoint IDO Use.............................................................. 741 E.5.2. Software Control of Root Port IDO Use............................................................. 742 ACKNOWLEDGEMENTS ..................................................................................................... 744