PCI EXPRESS BASE SPECIFICATION, REV. 23.0, V. .03
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4.3.3. Bit Rate and Coding Format............................................................................... 254
4.3.4. PLL and CDR Bandwidths.................................................................................. 254
4.3.5. Tx and Rx Equalization....................................................................................... 255
4.3.6. Channel Reach.................................................................................................... 255
4.3.7. Statistical Budgeting of Jitter.............................................................................. 256
4.3.8. Measurement Reference Planes.......................................................................... 256
4.4. PARAMETER TABLES.................................................................................................... 256
4.4.1. Major Tx Parameter Changes wrt. 5.0G ............................................................ 256
4.4.2. 8.0G Transmitter Parameter Table..................................................................... 257
4.4.3. 8.0G Receiver Parameter Table ......................................................................... 260
4.4.4. 8.0G Tx, Rx Parameters for Channel Simulation ............................................... 262
4.4.5. Refclk Parameters for 8.0G ................................................................................ 264
4.5. AREAS TO BE RESOLVED POST REV 0.3 ....................................................................... 265
4.5.1. Transmitter Specification.................................................................................... 265
4.5.2. Receiver Tolerancing.......................................................................................... 266
4.5.3. Channel Tolerancing .......................................................................................... 266
4.5.4. Scrambling Effects .............................................................................................. 267
4.5.5. Jitter Budgeting and Statistical Methods............................................................ 267
4.5.6. Support for long (up to 20”) Channels............................................................... 268
5. POWER MANAGEMENT .............................................................................................. 321
5.1. OVERVIEW ................................................................................................................... 321
5.1.1. Statement of Requirements.................................................................................. 322
5.2. LINK STATE POWER MANAGEMENT............................................................................. 322
5.3. PCI-PM SOFTWARE COMPATIBLE MECHANISMS......................................................... 327
5.3.1. Device Power Management States (D-States) of a Function.............................. 327
5.3.2. PM Software Control of the Link Power Management State.............................. 331
5.3.3. Power Management Event Mechanisms............................................................. 336
5.4. NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS....................................... 343
5.4.1. Active State Power Management (ASPM) .......................................................... 343
5.5. A
UXILIARY POWER SUPPORT....................................................................................... 359
5.5.1. Auxiliary Power Enabling................................................................................... 359
5.6. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 360
6. SYSTEM ARCHITECTURE .......................................................................................... 363
6.1. INTERRUPT AND PME SUPPORT ................................................................................... 363
6.1.1. Rationale for PCI Express Interrupt Model........................................................ 363
6.1.2. PCI Compatible INTx Emulation........................................................................ 364
6.1.3. INTx Emulation Software Model ........................................................................ 364
6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 364
6.1.5. PME Support....................................................................................................... 366
6.1.6. Native PME Software Model .............................................................................. 366
6.1.7. Legacy PME Software Model ............................................................................. 367
6.1.8. Operating System Power Management Notification........................................... 367
6.1.9. PME Routing Between PCI Express and PCI Hierarchies ................................ 367
6.2. ERROR SIGNALING AND LOGGING................................................................................ 368
6.2.1. Scope................................................................................................................... 368
