xilinxaxiinterconnect_AXIinterconnect资源-CSDN文库

fpga

5星 · 超过95%的资源需积分: 17 44 浏览量 2022-06-22 11:16:10 上传评论 1 收藏 2.42MB PDF 举报

资源详情

资源评论

AXI Interconnect v2.1

LogiCORE IP Product Guide

Vivado Design Suite

May 17, 2022

Xilinx is creating an environment where employees, customers,

and partners feel welcome and included. To that end, we’re

removing non-inclusive language from our products and related

collateral. We’ve launched an internal initiative to remove

language that could exclude people or reinforce historical biases,

including terms embedded in our software and IPs. You may still

find examples of non-inclusive language in our older products as

we work to make these changes and align with evolving industry

standards. Follow this link for more information.

AXI Interconnect Product Guide v2.1 2

PG059 May 17, 2022 www.xilinx.com

Table of Contents

IP Facts

Chapter 1: Overview

AXI Infrastructure Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

AXI Interconnect Core Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 2: Product Specification

Use Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Maximum Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Chapter 3: Designing with the Core

AXI Interconnect Core Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Design Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Chapter 4: Design Flow Steps

Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Send Feedback

AXI Interconnect Product Guide v2.1 4

PG059 May 17, 2022 www.xilinx.com Product Specification

Introduction

The Xilinx® LogiCORE™ IP AXI Interconnect

core connects one or more AXI

memory-mapped master devices to one or

more memory-mapped slave devices.

Note:

The AXI Interconnect core is intended for

memory-mapped transfers only. For AXI4-Stream

transfers, see the AXI4-Stream Infrastructure IP Suite

LogiCORE IP Product Guide (PG085) [Ref 1].

Features

The AXI Interconnect core is comprised of

multiple LogiCORE IP instances (infrastructure

cores). Each of the AXI4 memory-mapped

infrastructure cores that comprise the AXI

Interconnect core are fully described in this

document. The following features apply to the

AXI Interconnect core in general and to all

infrastructure cores described in this document

unless otherwise noted:

• AXI protocol compliant. Can be configured

to support AXI3, AXI4, and AXI4-Lite

protocols.

•Interface data widths:

AXI4 and AXI3: 32, 64, 128, 256, 512, or

1,024 bits

AXI4-Lite: 32 or 64 bits

• Address width: Up to 64 bits

• USER width (per channel): Up to 1,024 bits

• ID width: Up to 32 bits

• Support for Read-only and Write-only

masters and slaves, resulting in reduced

resource utilization.

IP Facts

LogiCORE IP Facts Table

Core Specifics

Supported

Device

Family

(1)

UltraScale+™,

UltraScale™,

7 Series FPGAs

Zynq®-7000

Supported

User Interfaces

AXI4, AXI4-Lite, AXI3

Resources See Table 2-1 6 through Table 2- 2 6 .

Provided with Core

Design Files Verilog and VHDL

Example

Design

Not Provided

Test Bench Not Provided

Constraints

File

Xilinx Design Constraints (XDC)

Simulation

Model

Not Provided

Supported

S/W Driver

N/A

Tested Design Flows

(2)

Design Entry Vivado® Design Suite

Simulation

For supported simulators, see the

Xilinx Design Tools: Release Notes Guide

Synthesis Vivado Synthesis

Support

Release Notes

and Known

Issues

Master Answer Records

: 54453

All Vivado IP

Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:

1. For a complete list of supported devices, see the Vivado IP

catalog. Support for the AXI Interconnect IP is not migrated

beyond the UltraScale+ family. AXI switching for the Versal

family and beyond should instead use the AXI Smartconnect

IP, which provides compatible functionality. For more

information, see PG247 [Ref 15]. Also, support does not

extend beyond the UltraScale+ family for any the AXI

infrastructure cores covered in this Product Guide, except AXI

2. For the supported versions of the tools, see the

Xilinx Design Tools: Release Notes Guide.

Send Feedback

AXI Interconnect Product Guide v2.1 5

PG059 May 17, 2022 www.xilinx.com

Chapter 1

Overview

The AXI Interconnect core can only be added to a Vivado® IP integrator block design in the

Vivado Design Suite. The Interconnect IP core represents a hierarchical design block

containing multiple LogiCORE™ IP instances (infrastructure cores) that become configured

and connected during your system design session. Each of the infrastructure cores can also

be added directly to a block design (outside of the AXI Interconnect core) or selected

directly from the Vivado IP Catalog and configured for use in an HDL design.

The AXI Interconnect core allows any mixture of AXI master and slave devices to be

connected to it, which can vary from one another in terms of data width, clock domain and

AXI sub-protocol (AXI4, AXI3, or AXI4-Lite). When the interface characteristics of any

connected master or slave device differ from those of the crossbar switch inside the

interconnect, the appropriate infrastructure cores are automatically inferred and connected

within the interconnect to perform the necessary conversions.

AXI Infrastructure Cores

The following IP cores, described in this document, can be included within each instance of

the AXI Interconnect core, depending on the configuration of AXI Interconnect core and its

connectivity in the IP integrator block design:

• AXI Crossbar connects one or more similar AXI memory-mapped masters to one or

more similar memory-mapped slaves.

• AXI Data Width Converter connects one AXI memory-mapped master to one AXI

memory-mapped slave having a wider or narrower datapath.

• AXI Clock Converter connects one AXI memory-mapped master to one AXI

memory-mapped slave operating in a different clock domain.

• AXI Protocol Converter connects one AXI4, AXI3 or AXI4-Lite master to one AXI slave

of a different AXI memory-mapped protocol.

• AXI Data FIFO connects one AXI memory-mapped master to one AXI memory-mapped

slave through a set of FIFO buffers.

• AXI Register Slice connects one AXI memory-mapped master to one AXI

memory-mapped slave through a set of pipeline registers, typically to break a critical

timing path.

• AXI MMU provides address range decoding and remapping services for AXI

Interconnect.

Send Feedback

剩余172页未读，继续阅读

评论收藏

内容反馈

本本纲目

2023-07-26

文档结构清晰，从基础概念到高级应用的讲解层次逐步深入，循序渐进，适合不同层次的读者阅读。

xilinx axi interconnect

评论5

最新资源

xilinx axi interconnect

评论5

最新资源

相关推荐

Xilinx_AXI_Xilinx_AXI-4verilog_

xilinx axi_uartlite资料

pg059-axi-interconnect xilinx

axi-apb-bridge_xilinx.pdf

axi-cdma.rar_AXI_AXI_CDMA_axi cdma_cdma vivado_xilinx cdma

pg059-axi-interconnect_fpga_pg059_axiinterconnect_AXI_

ds768_axi_interconnect.rar_AXI_axi-interconnect_axi_interconnect

xilinx-axidma 驱动模块 petalinux2020

Xilinx_axi手册整理.zip

Xilinx官方AXI DMA技术文档（PG021）

pg021_axi_dma.rar_AXI_AXI DMA_AXI DMA xilinx pg021_pg021

PCIE.rar_XILINX PCIE_pcie_pcie PIO_pcie axi spartan6_pcie xilinx

xapp1052.rar_AXI_AXI DMA_DMA axi_dma_xilinx xapp1052

xilinx zynq axi总线资料

Xilinx AXI_BRAM IP核

XILINX AXI-STREAM-FIFO 手册

XILINX FPGA AXI开发 参考文档

xilinx_axidma-master.rar_ZYNQ7000_axidma_chrdev_axidma测试_xilinx

xilinx-axidma-master DMA驱动

xilinx_axidma.zip

AXI_to_REG.rar_AXI_Xilinx_axi 转换_axi reg_forth4a8

XILINX ISE axi_uartlite IP核修改

XILINX axidma的BD工程以及对应的linux设备树

xapp1286_pcie_axi4_lite_bridge_PCIeaxi4_Xilinx_axi4_pcie_Bridge_

STM32CubeMx6.4.0版本+JRE安装包

KEIL5 常用stm32芯片包下载

ser2pl64.sys是电脑重要系统文件，主要用于串口转USB，描述：USB-to-Serial Cable Driver

CubeMX，6.11版本

XILINX FPGA AXI开发参考文档