AXI DMA v7.1
LogiCORE IP Product Guide
Vivado Design Suite
PG021 April 4, 2018
AXI DMA v7.1 2
PG021 April 4, 2018 www.xilinx.com
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: Product Specification
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Scatter Gather Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Multichannel DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 3: Designing with the Core
Typical System Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Chapter 5: Example Design
Implementing the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Test Bench for the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Send Feedback
AXI DMA v7.1 3
PG021 April 4, 2018 www.xilinx.com
Appendix A: Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Vivado Design Suite Debug Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Send Feedback
AXI DMA v7.1 4
PG021 April 4, 2018 www.xilinx.com Product Specification
PG021 April 4, 2018
Introduction
The Xilinx® LogiCORE™ IP AXI Direct Memory
Access (AXI DMA) core is a soft Xilinx IP core for
use with the Xilinx Vivado® Design Suite. The
AXI DMA provides high-bandwidth direct
memory access between memory and
AXI4-Stream target peripherals. Its optional
scatter/gather capabilities also offload data
movement tasks from the Central Processing
Unit (CPU).
Features
• AXI4 compliant
• Optional Scatter/Gather Direct Memory
Access (DMA) support
• AXI4 data width support of 32, 64, 128, 256,
512 and 1,024 bits
• AXI4-Stream data width support of 8, 16,
32, 64, 128, 256, 512 and 1,024 bits
• Optional Keyhole support
• Optional Data Re-Alignment support for
streaming data widths up to 512 bits
• Optional AXI Control and Status Streams
• Optional Micro DMA Support
• Support for up to 64-bit addressing
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family
(1)
1. For a complete list of supported devices, see the Vivado IP
catalog.
UltraScale+™
UltraScale™
Zynq®-7000 All Programmable SoC,
Xilinx 7 series FPGAs
Supported
User Interfaces
AXI4, AXI4-Lite, AXI4-Stream
Resources Performance and Resource Utilization web page
Provided with Core
Design Files VHDL
Example
Design
VHDL
Test Bench VHDL
Constraints
File
Delivered with IP Generation
Supported
S/W Drivers
(2)
2. Standalone driver information can be found in the Software
Development Kit (SDK) installation directory. See
xilinx_drivers.htm in
<install_directory>/SDK/<release>/data/embeddedsw/
doc/xilinx_drivers.htm.
Linux OS and driver support information is available from
the Xilinx Wiki page.
Standalone and Linux
Tested Design Flows
(3)
3. For the supported versions of the tools, see the
Xilinx Design Suite: Release Notes Guide.
Design Entry Vivado Design Suite
Simulation
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page.
Send Feedback
AXI DMA v7.1 5
PG021 April 4, 2018 www.xilinx.com
Chapter 1
Overview
The AXI Direct Memory Access (AXI DMA) IP core provides high-bandwidth direct memory
access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its optional
scatter gather capabilities also offload data movement tasks from the Central Processing
Unit (CPU) in processor-based systems. Initialization, status, and management registers are
accessed through an AXI4-Lite slave interface. Figure 1-1 illustrates the functional
composition of the core.
X-Ref Target - Figure 1-1
Figure 1-1: AXI DMA Block Diagram
DataMover
Registers
MM2S Cntl/Sts Logic
S2MM Cntl/Sts Logic
DataMover
Scatter/Gather
AXI4 Memory Map Read
AXI4-Lite
AXI4 Memory Map Write AXI4-Stream Slave (S2MM)
AXI4 Stream (S2MM)
AXI4 Memory Map Write/Read
AXI4 Control Stream (MM2S)
AXI4 Stream Master (MM2S)
x13225
Send Feedback
评论0