AR0330_Datasheet

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② Aptina AR0330: 13-Inch CMOS Digital Image Sensor Table of Contents Table of contents Features Applications........................... General Description Ordering Information General Description.∴∴ 翻D ·音 Functional Overview Working m oaes 8 HiSPi Power Supply Connections.... ·····.······ .12 Pin descriptions Sensor initialization 16 Power- Up Sequence∴. 16 Power- Down Sequence,,,,,,,…,,,,,,…,,,,. 18 Electrical characteristics 19 HiSPi Transmitter SLVS Electrical Specifications 23 HiVCM Electrical Specifications....... ,,,,,,,24 Electrical Definitions .............26 Timing Definitions..... ,,,,,,,,,,,,28 Transmitter Eve mask 29 Clock signal ···· 30 Sequencer ····· ,,,,,,,,,,,,,,,,,,,,,,,,,,,33 Sensor Pll 影鲁垂·····非 ·· ,,,,,,,,,,,,,33 VCO Dual Readout paths∴, 4 Parallel PlL Configuration .................... ,,,,,34 Serial PLL Configuration................... ∴.,,,,35 Pixel Output Interfaces 37 Parallel Interface ...,..,.,.... ,,,,37 Output Enable Control. ·.······. 3 Configuration of the Pixel Data Interface 37 High Speed Serial Pixel Data Interface, ............ ,,38 HiSPi Physical layer 39 DLL Timing adjustment 39 HiSPi Streaming mode Protocol layer 10 MIPI Interface,,,..... 41 Serial configuration 41 Pixel sensitivity .....,42 Gain Stages..... ,,,,,,45 Data pedestal.. ··.······· ,,,,,,,,,,,,,,,,,,,,46 Sensor readout 47 Image Acquisition Modes.... ·,· 47 Window control 47 Readout modes 47 Horizontal mirror 47 Vertical Fli ·鲁鲁·音 ,,,,,,,,,48 Subsampling 翻 49 Sensor frame rate ,,,,,,52 Row Period trow) .:.·· 53 Row Periods per frame ∴.,,,,,,.53 Slave mode ....54 Frame readout ,,,,,,,,,58 @2010 Aptina Imaging Corporation. All rights reserved ② Aptina AR0330: 13-Inch CMOS Digital Image Sensor Table of Contents Changing Sensor Modes......... Real- 'ime Context switching….“… Register Changes .:·:·· ,,,,,,,,,,,59 Lens Shading correction............ 春番D 6 Compression ···:·· 62 Test patterns 62 Solid color ∴.,62 Vertical Color bars 62 Walking ls 6 Two-Wire Serial Register Interface............. 63 Protocol ··.·.·.:··· .,63 Start Condition 翻春 .,63 Stop Condition ·········.· ··:········ ,,,,,63 Data Transfer ····.· 63 Slave Address/ Data Direction Byte.....,... ...,64 Message Byte 64 Acknowledge Bit∴ 64 No- Acknowledge Bit..……,,,…… 64 Typical sequence 64 Single rEAd From Random Location.............,.................. 65 Single rEAD From Current Location ............. ,,,,,,65 Sequential read, start From Random Location .............66 Sequential READ, Start From Current Location 66 Single write to Random Location ,,66 Sequential WriTE, Start at Random Location.......... ,,,,,67 Spectral Characteristics...... 鲁看, ∴.,,,,,.,68 Read the Sensor CRA Packages ·.::.···········.··:..···.···· ....72 CLCC Package 72 CSP Packages..... Package Orientation in Camera design..... Revision history....... 378 @2010 Aptina Imaging Corporation. All rights reserved ② Aptina ARO330 1/3-Inch CMOS Digital Image Sensor List of figures List of Figures Figure l: Block Diagram Figure2: Typical Configuration: Serial four-Lane hiSPi Interface.……………9 Figure 3: Typical Configuration: Serial MIPI 10 Figure 4: Typical Configuration: Parallel Pixel Data Interface..,..................11 Figure 5: CLCC Package Pin Descriptions..,.................. .15 Figure 6: Power Up Figure 7 Power down 18 Two-Wire Serial Interface Timing Parameters 21 Figure 9 I/O Timing diagram ,,,,,,,,,,21 Figure 10: Single-Ended and Differential Signals ,27 ....27 Figure 17: Relationship between Readout Clock and Peak Pixel Rate, ,... igure 11: DC Test Circuit Figure 12: Clock-to-Data Skew Timing Diagram 28 Figure 13: Differential Skew ∴.,29 Figure 14: Transmitter Eye Mask ·· Figure 15: Clock Duty Cycle ··· 30 Figure 16: Clock Jitter 33 Figure 18: Sensor Dual Readout Paths ,,,,,,,,34 Figure 19: PLL for the Parallel Interface 34 Figure 20: PlL for the serial Interface ······ 35 Figure 21: HiSPi Transmitter and Receiver Interface Block Diagram 38 Figure 22: Timing Diagram 39 Figure 23: Block Diagram of DlL Timing adjustment ,,,,,,,39 Figure 24: Delaying the clock lane with Respect to data lane ·.·· 40 Figure 25: Delaying data_lane with Respect to the clock lane. ,,,40 Figure 26: Integration Control in ERS Readout 42 Figure 27: Example of 8 33ms Integration in 166ms Frame ∴,,,,43 Figure 28: Row Read and row reset Showing Fine Integration 43 Figure 29: The Row Integration Time is Greater Than the Frame Readout Time Figure 30: Gain Stages in ARO330 Sensor.. ,,45 Figure 31: Effect of Horizontal Mirror on Readout Order.....,........,.........48 Figure 32: Effect of Vertical Flip on Readout order 48 Figure 33: Horizontal Binning in the ARo330 Sensor 49 Figure 34: Vertical Row Binning in the AR0330 Sensor ,49 Figure 35: Frame Period Measured in Clocks 52 Figure 36: Slave Mode Active State and Vertical Blanking 54 Figure 37: Slave Mode Example with Equal Integration and Frame Readout Periods 55 Figure 38: Slave Mode Example Where the Integration Period is half of the Frame Readout Period....56 Figure 39: Example of the Slave Mode with a Flat-field Illumination.........,.,....... 57 Figure 40: Example of the Sensor Output of a 2304 x 1296 Frame at 60 fps · 58 igure 41: Example of the Sensor Output of a 2304 x1296 Frame at 30 fps ................ 59 Figure 42: Example of Changing the Sensor from Context A to Context B................ 60 Figure 43: Before and After Signal 61 Figure 44: Single READ From Random Location 65 Figure 45: Single READ From Current Location ,,,,,,,65 Figure 46: Sequential READ, Start From Random Location ,,66 Figure 47: Sequential read, start From Current Location ,,,,,,,,,,,,,,,,66 Figure 48: Single WritE to Random Location ∴,,,,,,,,,,,,66 Figure 49: Sequential WrITE, Start at Random Location........................ 67 Figure 50: Bare Die Quantum Efficiency. ,68 Figure 51: CLCC Package.......... ,,72 Figure 52: CSP HiSPi Package Figure53: CSP Parallel/ MIPI Package Outline Drawing……、∵ 翻d ...74 igure54: Image Orientation With Relation To Camera Lens∴.∴……………7 Figure 55: First Clear Pixel and Pin Location ,,77 @2010 Aptina Imaging Corporation. All rights reserved ② Aptina AR0330: 1/3-Inch CMOS Digital Image Sensor List of tables List of tables Table 1 Available part numbers Table 2: Key Parameters ,,,,,,,,,,,,,,,,1 Table 3 Available Aspect Ratios in the Aro330 Sensor Table 4: Available Working Modes in the ARo330 Sensor Table 5 CLCC Package Pinout 883 Table 6: CSP (HiSPi/MIPI) Package Pinout 番省 14 Table 7 CSP(Parallel/MIPn) Package Pinout 14 able 8: Power-Up Sequence.............. ∴,,,,,,,17 Table 9 Power-Down Sequence 18 Table 10: DC Electrical Definitions and Characteristics(MIPI Mode ..19 Table ll: DC Electrical Definitions and characteristics(HiSPi Mode .,19 Absolute Maximum Ratings.……;…;…… 20 Table 13: Two-Wire Serial interface electrical characteristics 20 Table 14: 'Iwo-Wire Serial Interface Timing Specifications ,,,,,,,,,,,..,20 ble 15: I/O P 2 Table 16: I/O Timing 22 Table 17: Parallel i/o rise slew rate 22 Table 18: Power Supply and Operating Temperature......,.. 23 Table 19: SLVS Electrical DC Specification 23 Table 20: SLvs Electrical Timing specification ....,,,.,,,,,,,,...,,.,.,24 Table 21: HivCM Power Supply and operating Temperatures..,......... :··:··· 24 Table 22: HiVCM Electrical Voltage and Impedance Specification.. .,,,,,25 Table 23: HiVCM Electrical AC Specification..... ,,,26 Table 24: HiVCM Electrical AC Specification.,,,.. 32 able 25: PlL Parameters for the Parallel Interface.... ∴.....34 Table 26: Example PLL Configuration for the Parallel Interface ∴,35 Table 27: pll Parameters for the serial interface 36 Table 28: Example PLL Configurations for the Serial Interface Table 29: Output Enable Control ··:··:.··.:····:.··.····· 3 Table 30: Configuration of the Pixel Data Interface 37 ible 31: Recommended MIPI Timing Configuration ,,,,,,,42 able 32: Recommended Sensor Analog Gain Tables ,45 Table 33: Available Skip and Bin modes in the ARo330 Sensor .49 Table34: Configuration for Horizontal Subsampling.……… ,,,,,50 Table 35: Configuration for Vertical Subsampling ·····:···· 51 Table 36: Minimum Vertical Blanking Configuration 53 Table 37: Serial SYNC Codes included with each protocol included with the aro330 Sensor ............58 Table 38: List of Configurable registers for Context A and Context B ,,,,,,,60 Table 39:A-Law Compression Table for 12-10 bits.......... · ,,,,,,,62 Table 40: Test Pattern Modes ·· 62 Table4l: Chief Ray angle(CRA)12°.∴… ···:·· ,,,,,,,,69 Table 42: Chief Ray Angle(CRA)210. 70 Table 43: Chief Ray Angle( CrA)25 71 Table 44: CRA Value...... 71 Table 45: CSP (MIPI/HiSPi) Package Dimensions..........................75 Table 46: CSP(Parallel/ MIPI) Package Dimensions 75 @2010 Aptina Imaging Corporation. All rights reserved ② Aptina ARO330: 1/3-Inch CMOS Digital Image Sensor General Description General Description The aro330 can be operated in its default mode or programmed for frame size, expo sure, gain, and other parameters. The default mode output is a 2304 x 1296 image at 60 frames per second(fps). The sensor outputs 10-or 12-bit raw data, using either the parallel or serial (HiSPi, MIPn)output ports Functional overview The aro330 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (pll) that can generate all internal clocks from a single master input clock running between 6 and 64 MHz. The maximum output pixel rate is 196 Mp/s using a 4-lane HiSPi or MipI serial interface and 98 Mp/s using the parallel interface. Figure l shows a block diagram of the sensor Figure 1: Block Diagram Test Pattern Generator Clock 12-bt Analog Core Digital Core Output Data- Path Row Noise correction Compression(optional) PLL Black level correction Timing Lens Shading Correction Q Pixel Array Amplifiers Digital Gain Control Data Pedestal ADO 12-bit 10 or 12-b sisters 2-bit 8.10 12-bit Tw Parallel l/o MIPI 1/O HiSPi l/O PIXCLK. FV CLK P/N CP/N [11:]DATA [1: 4]P/N SLVS [3: 0]P/N Mp/s Max 196 Mp/s Max 196 Mp/s over 4 lanes over 4 lanes (588 Mbps/lane)(588 Mbps/lane) User interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 3. 4Mp active-pixel sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout Once a row has been read, the signal from the column is amplified in a column amplifier and then digitized in an analog-to-digital converter (ADC). The output from the adc is a 12-bit value for each pixel in the array. The adC output passes through a digital processing signal chain(which provides further data path corrections and applies gital gain 7 @2010 Aptina Imaging Corporation. All rights reserved ② Aptina ARO330 1/3-Inch CMOS Digital Image Sensor Working Modes Working Modes The aro330 sensor working modes are specified from the following aspect ratios Table 3 Available aspect Ratios in the aro330 Sensor Aspect ratio Sensor Array Usage 4:3 Still format # 2256()X1296) 16:10 Still format #2 2256(H)x1504() 16:9 HD Format 2304(H)×1296) (196 Mp/ s)the sensor must use the 4-lane HiSPior MIPIinterface The sensor weed The ARo330 supports the following working modes. To operate the sensor at full sp operate at half-speed (98 Mp/s)when using the parallel interface Table 4: Available Working Modes in the ARo330 Sensor FPS Active readout Sensor Output (4-Lane MIPI/HiSPi(Parallel Sub Mode Aspect Ratio Window Resolution Interface Interface) sampling FOV 1080p +EIS 69 2304X1296 2304X1296 60 n/a 100% 30 30 100% 3M Still 4:3 2048×1536 2048×1536 30 25 100% 3:2 2256X1504 2256X1504 25 100% WVGA+ EIs 169 2304X1296 1152X648 60 60 2X2 100% WVGA+ els 9 2304X1296 1152X648 120 N/A 2X2 100% Slow-motion VGA Video 16:10 2256X1440 752X480 60 60 3x3 96% VGA Video 16:10 2256X1440 752X480 215 107 96% Slow-motion @2010 Aptina Imaging Corporation. All rights reserved ② Aptina ARO330 1/3-Inch CMOS Digital Image Sensor Working Modes gure 2 Fig Typical Configuration: Serial Four-Lane HiSPi Interface gital Digital 1/0 Ce PLL Analog Analo powerI power power power- power power1 SLVSO N Master clock SLVSI P EXTCLK 6-64MHz) SLVS1 N TRIGGER SLVS2 N SCLK SLVS3 controller From (HiSPi-serial interface) SLVS3 RESET BAR SLVSC SLVSC FLASH TEST SHUTTER DGND GND SLVS AGN Digital Analo grou oun VDD HISPI TX VDD IO VDD VDD HISPI VDD PLL VAA VAAPⅨX 1oF0.11.o山01u1.ou F01叫1.0u山0100.1山1ou0 Notes: 1. All power supplies must be adequately decoupled Aptina recommends having 1.OuF and 0.1uF decou- pling capacitors for every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_ PIX, VDD_PLL, VDD_IO, and VDD. Actual values and results may vary depending on layout iderati 2. To allow for space constraints, Aptina recommends having 0. luF decoupling capacitor inside the mod ule as close to the pads as possible. In addition, place a 10uF capacitor for each supply off-module but close to each supply 3. Aptina recommends a resistor value of 1.5kQ2, but a greater value may be used for slower two-wire speed 4. The pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times 5. Aptina recommends that analog power planes are placed in a manner such that coupling with the digi tal power planes is minimized 6. test pin should be tied to dgNd 7. Set High VCM(ROX306E[9])to o(default) to use the VDD HiSPi TX in the range of 0.4-0.8V.Set High VCM to 1 to use a range of 1.7-1.9V 8. The package pins or die pads used for the MiPl data and clock as well as the parallel interface must be left floating 9. The VDD_ MIPl package pin and sensor die pad should be connected to a 2. 8V supply as VDD MIPI is tied to the VDD PLL supply both in the package routing and also within the sensor die itself 10. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating 11. If the tRiGger or OE BAR pins or pads are not used, then they should be tied to DGND 12. The GND SLVS pad must be tied to DGND. It is connected this way in the ClCc and CSP packages @2010 Aptina Imaging Corporation. All rights reserved ② Aptina ARO330 1/3-Inch CMOS Digital Image Sensor Working Modes Figure 3: Typical Configuration: Serial MIPI Digital Digital Core power powerl power pe ower power VDD IO VDD A VAAVAA PIX DATA1 N aster cloc (6-64MHz) EXTCLK DATA3 P OE BAR DATA3 N TO TRIGGER DATA4 P controlle DATA4 N (MIPI-serial interface) controller S SDATA CLK P RESET BAR CLK N SHUTTER TEST FLASH DANI AGND g alog ound VDD IO VCD VDD VAA VAAPⅩ 10uF0.1 1.0uF 0.1uH.1.0uF OluF 1.OuF O1uF 1.0uF 0luF Notes: 1. All power supplies must be adequately decoupled Aptina recommends having 1.OuF and 0. 1uF decou ling capacitors for every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA PIX, VDD PLL, VDD MIPL, VDD IO, and VDD. Actual values and results may vary depending on ayout and de sign considerations To allow for space constraints, Aptina recommends having O 1uF decoupling capacitor inside the mod ule as close to the pads as possible. In addition, place a 10uF capacitor for each supply off-module but close to each supply 3. Aptina recommends a resistor value of 1.5kQ, but a greater value may be used for slower two-wire speed 4. The pull-up resistor is not required if the controller drives a valid logic level on Sclk at all times 5. Aptina recommends that analog power planes are placed in a manner such that coupling with the digi- tal power planes is minimized 6. tEST pin must be tied to dgnd for the mlpl configuration 7. Aptina recommends that gnd Mlpl be tied to dgnd 8. VDD MIPl is tied to VDD PLL in both the CLCC and the CSP package Aptina strongly recommends that VDD MIPl must be connected to a VDD PLL in a module design since VDD PLl and VDD_ MlPl are tied together in the die 9. The package pins or die pads used for the HiSPi data and clock as well as the parallel interface must be left floating 10. HiSPi Power Supplies(VDD HiSPi and VDD HiSPi tx) can be tied to ground 11. If the ShUTTER or FLASH pins or pads are not used, then they must be left floating 12. If the trigger or oe bar pins or pads are not used then they should be tied to dgnd 10 @2010 Aptina Imaging Corporation. All rights reserved

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