################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
没有合适的资源?快使用搜索试试~ 我知道了~
温馨提示
内容概述:杭电计算机组成原理实验十一,基于FPGA的芯片设计,RISC-V模型机设计(R型、I型、U型基本运算指令、访存指令、转移指令,共37条),连接运算器、存储器、寄存器堆、控制器,包含源代码、仿真代码、管脚配置 开发环境:vivado2018,vivado2022也兼容vivado2018 适合人群:有数字电路基础,正在学习计算机组成原理课程的大学学生,有一定的vivado软件的使用经验
资源推荐
资源详情
资源评论
收起资源包目录
基于FPGA的芯片设计,RISC-V模型机设计(R型、I型、U型基本运算指令、访存指令、转移指令,共37条 (793个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 23KB
elaborate.bat 946B
compile.bat 840B
simulate.bat 807B
runme.bat 229B
runme.bat 229B
runme.bat 229B
exam-8.bit 3.65MB
exam-11.bit 3.65MB
RIU_CPU_top.bit 3.65MB
exam-10.bit 3.65MB
xsim_1.c 18KB
RIUS_data.coe 308B
RIUS_data.coe 308B
RIUS_data.coe 308B
RIUS_data.coe 308B
RIUS_data.coe 308B
RIUS_data.coe 308B
RIUS_data.coe 308B
RIUS_data.coe 308B
RIUS_data.coe 308B
RIUS_data.coe 308B
RIUS_data.coe 308B
ip.coe 208B
ip.coe 208B
ip.coe 208B
ip.coe 208B
ip.coe 208B
ip.coe 208B
ip.coe 208B
ip.coe 208B
ip.coe 208B
ip.coe 208B
ip.coe 208B
xsim.dbg 155KB
RIU_CPU_top_routed.dcp 1.37MB
RIU_CPU_top_placed.dcp 1.08MB
RIU_CPU_top_opt.dcp 645KB
RIU_CPU_top.dcp 468KB
DM.dcp 36KB
DM.dcp 36KB
DM.dcp 36KB
DM.dcp 36KB
DM.dcp 36KB
DM.dcp 36KB
DM.dcp 36KB
DM.dcp 36KB
DM.dcp 35KB
DM.dcp 35KB
DM.dcp 35KB
DM.dcp 35KB
DM.dcp 35KB
DM.dcp 35KB
DM.dcp 35KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 29KB
IM.dcp 28KB
IM.dcp 28KB
compile.do 755B
compile.do 755B
compile.do 721B
compile.do 721B
compile.do 671B
compile.do 671B
compile.do 657B
compile.do 657B
simulate.do 319B
simulate.do 319B
simulate.do 307B
simulate.do 307B
simulate.do 307B
simulate.do 307B
elaborate.do 191B
elaborate.do 191B
simulate.do 181B
simulate.do 181B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
共 793 条
- 1
- 2
- 3
- 4
- 5
- 6
- 8
资源评论
AllinTome
- 粉丝: 3377
- 资源: 5
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功