################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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基于FPGA的芯片设计,RISC-V存储器设计(源代码) (377个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 23KB
elaborate.bat 944B
compile.bat 838B
simulate.bat 804B
runme.bat 229B
runme.bat 229B
runme.bat 229B
Memory_top.bit 3.65MB
xsim_1.c 9KB
xsim_1.c 9KB
ip.coe 233B
ip.coe 233B
ip.coe 233B
ip.coe 233B
ip.coe 233B
ip.coe 233B
ip.coe 233B
ip.coe 233B
ip.coe 233B
ip.coe 233B
ip.coe 233B
xsim.dbg 78KB
xsim.dbg 74KB
Memory_top_routed.dcp 220KB
Memory_top_placed.dcp 203KB
Memory_top_opt.dcp 178KB
RAM_B.dcp 35KB
RAM_B.dcp 35KB
RAM_B.dcp 35KB
RAM_B.dcp 35KB
RAM_B.dcp 35KB
RAM_B.dcp 35KB
Memory_top.dcp 34KB
compile.do 752B
compile.do 718B
compile.do 668B
compile.do 654B
simulate.do 325B
simulate.do 316B
simulate.do 316B
elaborate.do 197B
simulate.do 187B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 144KB
xsimk.exe 138KB
run.f 495B
run.f 475B
usage_statistics_webtalk.html 29KB
.xsim_webtallk.info 65B
.xsim_webtallk.info 64B
xsim.ini 23KB
xsim.ini 22KB
xsimSettings.ini 1KB
xsimSettings.ini 1KB
vivado_3256.backup.jou 19KB
vivado_15848.backup.jou 1020B
vivado_14096.backup.jou 988B
webtalk_16980.backup.jou 851B
webtalk_14852.backup.jou 851B
webtalk.jou 850B
webtalk_3480.backup.jou 850B
vivado_14524.backup.jou 803B
vivado.jou 802B
vivado_22408.backup.jou 770B
vivado.jou 769B
vivado.jou 764B
vivado.jou 763B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
vivado_3256.backup.log 91KB
runme.log 32KB
runme.log 30KB
runme.log 21KB
vivado_15848.backup.log 2KB
vivado_14096.backup.log 2KB
vivado_14524.backup.log 1KB
vivado.log 1KB
elaborate.log 1KB
webtalk_14852.backup.log 981B
webtalk_16980.backup.log 981B
webtalk_3480.backup.log 980B
webtalk.log 980B
summary.log 902B
summary.log 902B
summary.log 902B
summary.log 902B
summary.log 902B
summary.log 902B
summary.log 902B
summary.log 902B
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