################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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基于FPGA的芯片设计,RISC-V取指令与指令译码实验 (513个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 23KB
elaborate.bat 936B
compile.bat 830B
simulate.bat 792B
runme.bat 229B
runme.bat 229B
runme.bat 229B
Instruct_Unit_top.bit 3.65MB
xsim_1.c 10KB
xsim_1.c 9KB
move.coe 307B
move.coe 307B
move.coe 307B
move.coe 307B
move.coe 307B
move.coe 307B
move.coe 307B
move.coe 307B
move.coe 307B
move.coe 307B
move.coe 190B
ip.coe 100B
ip.coe 100B
xsim.dbg 79KB
xsim.dbg 76KB
Instruct_Unit_top_routed.dcp 301KB
Instruct_Unit_top_placed.dcp 269KB
Instruct_Unit_top_opt.dcp 215KB
Instruct_Unit_top.dcp 74KB
blk_mem_gen_0.dcp 37KB
IM.dcp 35KB
blk_mem_gen_0.dcp 35KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
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blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
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blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
compile.do 775B
compile.do 741B
compile.do 691B
compile.do 677B
simulate.do 341B
simulate.do 340B
simulate.do 340B
elaborate.do 213B
simulate.do 203B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 145KB
xsimk.exe 142KB
run.f 518B
run.f 498B
usage_statistics_webtalk.html 30KB
.xsim_webtallk.info 65B
.xsim_webtallk.info 65B
xsim.ini 23KB
xsim.ini 22KB
xsimSettings.ini 1KB
xsimSettings.ini 1KB
vivado_6776.backup.jou 3KB
vivado_3676.backup.jou 2KB
webtalk_14140.backup.jou 914B
webtalk_10524.backup.jou 914B
webtalk.jou 903B
webtalk_21116.backup.jou 903B
vivado.jou 861B
vivado.jou 854B
vivado.jou 840B
vivado_13668.backup.jou 840B
vivado.jou 835B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 54KB
runme.log 33KB
runme.log 27KB
vivado_6776.backup.log 8KB
vivado_3676.backup.log 3KB
vivado.log 2KB
elaborate.log 1KB
xvlog.log 1KB
compile.log 1KB
webtalk_10524.backup.log 1KB
webtalk_14140.backup.log 1KB
webtalk_21116.backup.log 1KB
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