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PCI Express PHY
LogiCORE IP Product Guide
Vivado Design Suite
PG239 (v1.0) June 3, 2022
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Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Features........................................................................................................................................4
IP Facts..........................................................................................................................................5
Chapter 2: Overview......................................................................................................6
Applications..................................................................................................................................7
Unsupported Features................................................................................................................7
Licensing and Ordering.............................................................................................................. 8
Chapter 3: Product Specification........................................................................... 9
Performance and Resource Use................................................................................................9
Port Descriptions.......................................................................................................................10
Chapter 4: Designing with the Core................................................................... 22
Clocking...................................................................................................................................... 22
Resets..........................................................................................................................................23
MAC Requirements................................................................................................................... 24
Equalization Sequences............................................................................................................24
Chapter 5: Design Flow Steps.................................................................................28
Customizing and Generating the Core...................................................................................28
Constraining the Core...............................................................................................................35
Simulation.................................................................................................................................. 37
Synthesis and Implementation................................................................................................37
Chapter 6: Example Design..................................................................................... 38
Overview.....................................................................................................................................38
Simulating the Example Design.............................................................................................. 38
Appendix A: Upgrading............................................................................................. 40
Appendix B: Debugging.............................................................................................41
Finding Help on Xilinx.com...................................................................................................... 41
PG239 (v1.0) June 3, 2022 www.xilinx.com
PCI Express PHY 2
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Debug Tools............................................................................................................................... 42
Appendix C: Additional Resources and Legal Notices............................. 43
Xilinx Resources.........................................................................................................................43
Documentation Navigator and Design Hubs.........................................................................43
References..................................................................................................................................43
Revision History.........................................................................................................................44
Please Read: Important Legal Notices................................................................................... 45
PG239 (v1.0) June 3, 2022 www.xilinx.com
PCI Express PHY 3
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Chapter 1
Introduction
The Xilinx
®
PCIe PHY IP is a building block IP that allows for a PCI Express
®
MAC to be built as
so IP in the FPGA fabric.
The Vivado
®
IP catalog does not allow generaon of this IP for all UltraScale™ and UltraScale+™
devices; however, if a device is selected and has the same transceiver type as the desired device
(UltraScale GTH, UltraScale+ GTH or UltraScale+ GTY), the IP can then be migrated to the
desired part.
Currently, the IP can be generated for the following devices:
• UltraScale+: ZU9EG (GTH), VU3P (GTY), and VU9P(GTY).
• UltraScale: KU040 (GTH), KU115 (GTH), VU440 (GTH), and VU440 ES2 (GTH).
Note:
•
When the IP is generated for a VU440 ES2 device, this IP should not be migrated to other devices.
•
While some UltraScale devices contain GTYs, this IP does not support GTY in the UltraScale family.
Features
• Gen1 (2.5 GT/s), Gen2 (5.0 GT/s), Gen3 (8.0 GT/s), and Gen4 (16 GT/s) speeds are supported.
• UltraScale devices support 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s line rates with x1, x2, x4, x8 lane
operaon.
• UltraScale+ devices support 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s line rates with x1, x2, x4, x8, x16
lane operaon. Addionally, they support 16.0 GT/s line rate with x1, x2, x4, x8 lane
operaon.
• Supports P0s low power state when congured as Gen1 or Gen2 only.
• Supports synchronous and asynchronous applicaons.
• Rate change between Gen1 and Gen2 is a xed datapath implementaon.
• Rate change between Gen3 and Gen4 is a xed PCLK implementaon.
• Low latency enabled by bypassing TX buer.
Chapter 1: Introduction
PG239 (v1.0) June 3, 2022 www.xilinx.com
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• Equalizaon sequence is part of the GT Quad in Versal devices provided Xilinx MAC is used.
For any third party MAC sll the equalizaon is part of the PHY IP.
IP Facts
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family
1
UltraScale+™, UltraScale™
Supported User Interfaces N/A
Resources Performance and Resource Use
Provided with Core
Design Files Verilog
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx
®
Design Constraints (XDC)
Simulation Model Verilog
Supported S/W Driver N/A
Tested Design Flows
2
Design Entry Vivado
®
Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 66988
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado
®
IP catalog.
2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
Chapter 1: Introduction
PG239 (v1.0) June 3, 2022 www.xilinx.com
PCI Express PHY 5
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