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mipi-D-PHY-specification-v1-2
MIPI Alliance 是一个行业组织,旨在推动移动和移动设备行业的发展。该组织制定了一系列标准规范,以确保移动设备和组件之间的互通性和兼容性。其中,D-PHY specification是MIPI Alliance制定的接口规范之一,用于定义高speed数字接口的物理层规范。
D-PHY specification是MIPI Alliance为满足高速数据传输的需求而制定的规范,旨在提供一个高speed、低power consumption的数字接口解决方案。该规范定义了数字接口的物理层规范,包括信号电压、时钟频率、数据传输速率等参数。
D-PHY specification版本1.2是MIPI Alliance于2014年发布的最新版本,该版本对之前的版本进行了更新和改进,进一步提高了数字接口的性能和可靠性。
MIPI Alliance制定的D-PHY specification具有以下特点:
* 高speed数据传输速率:D-PHY specification支持高速数据传输,最高可达2.5Gb/s。
* 低power consumption:D-PHY specification设计了低power consumption的数字接口,降低了设备的功耗。
* 高可靠性:D-PHY specification具有高可靠性,能够确保数据传输的稳定性和可靠性。
D-PHY specification在移动设备和组件中的应用非常广泛,例如在智能手机、平板电脑、电视机等设备中都可能使用D-PHY specification来实现高速数据传输。
MIPI Alliance还制定了其他相关的规范,例如MIPI CSI-2、MIPI DSI-2、MIPI C-PHY等,共同构成了MIPI Alliance的接口规范系列。这些规范共同作用,提供了一个完整的接口解决方案,能够满足移动设备和组件之间的高速数据传输需求。
MIPI Alliance的D-PHY specification是移动设备和组件之间高速数据传输的重要规范之一,对于移动设备和组件的发展产生了深远的影响。
Specification for
D-PHY
Version
1.2
01 August
2014
MIPI Board Adopted 10 September
2014
This document is subject to further edit
orial and technical development.
Copyright © 2007-2014 MIPI Alliance, Inc.
All rights reserved.
Confidential
Specification for D-PHY Version 1.2
01-Aug-2014
NOTICE OF DISCLAIMER
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled
by any of the authors or developers of this material or MIPI
®
. The material contained herein is provided on
an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS
AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all
other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if
any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of
accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of
negligence.
All materials contained herein are protected by copyright laws, and may not be reproduced, republished,
distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express
prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related
trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and
cannot be used without its express prior written permission.
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD
TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY
AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR
MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS
OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER
CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY
OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,
WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is
further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the
contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;
and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance
with the contents of this Document. The use or implementation of the contents of this Document may
involve or require the use of intellectual property rights (“IPR”) including (but not limited to) patents,
patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI
does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any
IPR or claims of IPR as respects the contents of this Document or otherwise.
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:
MIPI Alliance, Inc.
c/o IEEE-ISTO
445 Hoes Lane
Piscataway, NJ 08854
Attn: Board Secretary
ii Copyright © 2007-2014 MIPI Alliance, Inc.
All rights reserved.
Confidential
Version 1.2 Specification for D-PHY
01-Aug-2014
Contents
Contents ............................................................................................................................ iii
Figures .............................................................................................................................. vii
Tables ...................................................................................................................................x
Release History ................................................................................................................ xii
1 Introduction .................................................................................................................1
1.1 Scope ............................................................................................................................... 1
1.2 Purpose ............................................................................................................................ 2
2 Terminology .................................................................................................................3
2.1 Use of Special Terms ....................................................................................................... 3
2.2 Definitions ....................................................................................................................... 3
2.3 Abbreviations ................................................................................................................... 4
2.4 Acronyms ......................................................................................................................... 4
3 References ....................................................................................................................6
4 D-PHY Overview .........................................................................................................7
4.1 Summary of PHY Functionality ...................................................................................... 7
4.2 Mandatory Functionality ................................................................................................. 7
5 Architecture .................................................................................................................8
5.1 Lane Modules .................................................................................................................. 8
5.2 Master and Slave .............................................................................................................. 9
5.3 High Frequency Clock Generation .................................................................................. 9
5.4 Clock Lane, Data Lanes and the PHY-Protocol Interface ................................................ 9
5.5 Selectable Lane Options ................................................................................................ 10
5.6 Lane Module Types ....................................................................................................... 12
5.6.1 Unidirectional Data Lane ........................................................................................... 13
5.6.2 Bi-directional Data Lanes ........................................................................................... 13
5.6.3 Clock Lane.................................................................................................................. 14
5.7 Configurations ............................................................................................................... 14
5.7.1 Unidirectional Configurations .................................................................................... 16
5.7.2 Bi-Directional Half-Duplex Configurations ............................................................... 18
5.7.3 Mixed Data Lane Configurations ............................................................................... 19
6 Global Operation .......................................................................................................20
6.1 Transmission Data Structure .......................................................................................... 20
6.1.1 Data Units ................................................................................................................... 20
6.1.2 Bit order, Serialization, and De-Serialization ............................................................. 20
6.1.3 Encoding and Decoding ............................................................................................. 20
6.1.4 Data Buffering ............................................................................................................ 20
6.2 Lane States and Line Levels .......................................................................................... 20
6.3 Operating Modes: Control, High-Speed, and Escape .................................................... 21
6.4 High-Speed Data Transmission ..................................................................................... 21
6.4.1 Burst Payload Data ..................................................................................................... 21
6.4.2 Start-of-Transmission ................................................................................................. 22
6.4.3 End-of-Transmission .................................................................................................. 22
6.4.4 HS Data Transmission Burst....................................................................................... 22
Copyright © 2007-2014 MIPI Alliance, Inc. iii
All rights reserved.
Confidential
Specification for D-PHY Version 1.2
01-Aug-2014
6.5 Bi-directional Data Lane Turnaround ............................................................................ 24
6.6 Escape Mode .................................................................................................................. 27
6.6.1 Remote Triggers ......................................................................................................... 28
6.6.2 Low-Power Data Transmission .................................................................................. 28
6.6.3 Ultra-Low Power State ............................................................................................... 29
6.6.4 Escape Mode State Machine ...................................................................................... 29
6.7 High-Speed Clock Transmission ................................................................................... 31
6.8 Clock Lane Ultra-Low Power State ............................................................................... 36
6.9 Global Operation Timing Parameters ............................................................................ 38
6.10 System Power States ...................................................................................................... 42
6.11 Initialization ................................................................................................................... 42
6.12 Calibration ..................................................................................................................... 42
6.13 Global Operation Flow Diagram ................................................................................... 46
6.14 Data Rate Dependent Parameters (informative) ............................................................ 47
6.14.1 Parameters Containing Only UI Values .................................................................. 48
6.14.2 Parameters Containing Time and UI values ........................................................... 48
6.14.3 Parameters Containing Only Time Values .............................................................. 48
6.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent ..... 49
7 Fault Detection ..........................................................................................................50
7.1 Contention Detection ..................................................................................................... 50
7.2 Sequence Error Detection .............................................................................................. 50
7.2.1 SoT Error .................................................................................................................... 51
7.2.2 SoT Sync Error ........................................................................................................... 51
7.2.3 EoT Sync Error ........................................................................................................... 51
7.2.4 Escape Mode Entry Command Error .......................................................................... 51
7.2.5 LP Transmission Sync Error ....................................................................................... 51
7.2.6 False Control Error ..................................................................................................... 51
7.3 Protocol Watchdog Timers (informative) ...................................................................... 51
7.3.1 HS RX Timeout .......................................................................................................... 51
7.3.2 HS TX Timeout .......................................................................................................... 51
7.3.3 Escape Mode Timeout ................................................................................................ 51
7.3.4 Escape Mode Silence Timeout ................................................................................... 51
7.3.5 Turnaround Errors ...................................................................................................... 52
8 Interconnect and Lane Configuration .....................................................................53
8.1 Lane Configuration ........................................................................................................ 53
8.2 Boundary Conditions ..................................................................................................... 53
8.3 Definitions ..................................................................................................................... 53
8.4 S-parameter Specifications ............................................................................................ 54
8.5 Characterization Conditions .......................................................................................... 54
8.6 Interconnect Specifications ............................................................................................ 54
8.6.1 Differential Characteristics ......................................................................................... 55
8.6.2 Common-mode Characteristics .................................................................................. 56
8.6.3 Intra-Lane Cross-Coupling ......................................................................................... 56
8.6.4 Mode-Conversion Limits ............................................................................................ 56
8.6.5 Inter-Lane Cross-Coupling ......................................................................................... 56
8.6.6 Inter-Lane Static Skew ............................................................................................... 57
8.7 Driver and Receiver Characteristics .............................................................................. 57
8.7.1 Differential Characteristics ......................................................................................... 57
8.7.2 Common-Mode Characteristics .................................................................................. 58
iv Copyright © 2007-2014 MIPI Alliance, Inc.
All rights reserved.
Confidential
Version 1.2 Specification for D-PHY
01-Aug-2014
8.7.3 Mode-Conversion Limits ............................................................................................ 59
8.7.4 Inter-Lane Matching ................................................................................................... 59
9 Electrical Characteristics .........................................................................................60
9.1 Driver Characteristics .................................................................................................... 61
9.1.1 High-Speed Transmitter .............................................................................................. 61
9.1.2 Low-Power Transmitter .............................................................................................. 66
9.2 Receiver Characteristics ................................................................................................ 69
9.2.1 High-Speed Receiver .................................................................................................. 69
9.2.2 Low-Power Receiver .................................................................................................. 71
9.3 Line Contention Detection ............................................................................................. 72
9.4 Input Characteristics ...................................................................................................... 73
10 High-Speed Data-Clock Timing ............................................................................74
10.1 High-Speed Clock Timing ............................................................................................. 74
10.2 Forward High-Speed Data Transmission Timing .......................................................... 75
10.2.1 Data-Clock Timing Specifications.......................................................................... 76
10.3 Reverse High-Speed Data Transmission Timing ........................................................... 77
11 Regulatory Requirements ......................................................................................79
Annex A Logical PHY-Protocol Interface Description (informative) ...................80
A.1 Signal Description ......................................................................................................... 80
A.2 High-Speed Transmit from the Master Side .................................................................. 87
A.3 High-Speed Receive at the Slave Side ........................................................................... 87
A.4 High-Speed Transmit from the Slave Side .................................................................... 88
A.5 High-Speed Receive at the Master Side ........................................................................ 88
A.6 Low-Power Data Transmission ...................................................................................... 89
A.7 Low-Power Data Reception ........................................................................................... 89
A.8 Turn-around ................................................................................................................... 90
A.9 Calibration ..................................................................................................................... 91
Annex B Interconnect Design Guidelines (informative) ........................................93
B.1 Practical Distances ......................................................................................................... 93
B.2 RF Frequency Bands: Interference ................................................................................ 93
B.3 Transmission Line Design ............................................................................................. 93
B.4 Reference Layer ............................................................................................................. 93
B.5 Printed-Circuit Board ..................................................................................................... 94
B.6 Flex-foils ........................................................................................................................ 94
B.7 Series Resistance ........................................................................................................... 94
B.8 Connectors ..................................................................................................................... 94
Annex C 8b9b Line Coding for D-PHY (normative) ..............................................95
C.1 Line Coding Features ..................................................................................................... 96
C.1.1 Enabled Features for the Protocol .......................................................................... 96
C.1.2 Enabled Features for the PHY ................................................................................ 96
C.2 Coding Scheme .............................................................................................................. 96
C.2.1 8b9b Coding Properties .......................................................................................... 96
C.2.2 Data Codes: Basic Code Set ................................................................................... 96
C.2.3 Comma Codes: Unique Exception Codes .............................................................. 97
C.2.4 Control Codes: Regular Exception Codes .............................................................. 98
C.2.5 Complete Coding Scheme ...................................................................................... 98
Copyright © 2007-2014 MIPI Alliance, Inc. v
All rights reserved.
Confidential
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