################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA XC7A35T实现光纤接口8B10B测试(Verilog HDL实现).zip
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FPGA XC7A35T实现光纤接口8B10B测试(Verilog HDL实现).zip (707个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
gtwizard_0_exdes.bit 2.09MB
waveform.csv 25KB
waveform.csv 22KB
gt_rom_init_rx.dat 11KB
gt_rom_init_rx.dat 11KB
gt_rom_init_tx.dat 11KB
gt_rom_init_tx.dat 11KB
xsim.dbg 904B
xsim.dbg 784B
gtwizard_0_exdes_routed.dcp 3.27MB
gtwizard_0_exdes_physopt.dcp 2.87MB
gtwizard_0_exdes_placed.dcp 2.87MB
gtwizard_0_exdes_opt.dcp 2.27MB
ila_1.dcp 643KB
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ila_1.dcp 641KB
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dbg_hub.dcp 361KB
gtwizard_0.dcp 173KB
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gtwizard_0.dcp 172KB
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gtwizard_0_exdes.dcp 96KB
clk_wiz_0.dcp 10KB
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waveform.dmp 45KB
waveform.dmp 37KB
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elaborate.do 185B
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