FPGAXC7A35T实现RS485串口通信驱动（VerilogHDL实现）.zip_fpga实现rs485串口通信资源-CSDN文库

共113个文件

pb：16个

rst：16个

xml：14个

版权申诉

FPGA

XC7A35T

VerilogHDL

驱动程序

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FPGA XC7A35T实现RS485串口通信驱动（Verilog HDL实现）.zip （113个子文件）

__synthesis_is_complete__ 0B

runme.bat 229B

rs485_uart_top.bit 2.09MB

rs485_uart_top_routed.dcp 207KB

rs485_uart_top_placed.dcp 191KB

rs485_uart_top_opt.dcp 155KB

rs485_uart_top.dcp 42KB

libps7.dll 460KB

libremoteport.dll 361KB

ps7_init.html 1.96MB

usage_statistics_webtalk.html 36KB

vivado.jou 792B

vivado.jou 787B

ISEWrap.js 8KB

rundef.js 1KB

runme.log 31KB

runme.log 24KB

rs485_uart_top.lpr 343B

vivado.pb 41KB

place_design.pb 18KB

route_design.pb 14KB

opt_design.pb 12KB

write_bitstream.pb 4KB

init_design.pb 3KB

rs485_uart_top_power_summary_routed.pb 723B

rs485_uart_top_utilization_placed.pb 276B

rs485_uart_top_utilization_synth.pb 276B

vivado.pb 149B

rs485_uart_top_timing_summary_routed.pb 106B

rs485_uart_top_methodology_drc_routed.pb 52B

rs485_uart_top_route_status.pb 44B

rs485_uart_top_drc_routed.pb 37B

rs485_uart_top_drc_opted.pb 37B

rs485_uart_top_bus_skew_routed.pb 30B

rs485_uart_top_io_placed.rpt 146KB

rs485_uart_top_timing_summary_routed.rpt 93KB

rs485_uart_top_clock_utilization_routed.rpt 11KB

rs485_uart_top_utilization_placed.rpt 9KB

rs485_uart_top_power_routed.rpt 8KB

rs485_uart_top_utilization_synth.rpt 7KB

rs485_uart_top_control_sets_placed.rpt 4KB

rs485_uart_top_methodology_drc_routed.rpt 3KB

rs485_uart_top_drc_routed.rpt 2KB

rs485_uart_top_drc_opted.rpt 2KB

rs485_uart_top_bus_skew_routed.rpt 940B

rs485_uart_top_route_status.rpt 588B

rs485_uart_top_timing_summary_routed.rpx 78KB

rs485_uart_top_power_routed.rpx 60KB

rs485_uart_top_methodology_drc_routed.rpx 2KB

rs485_uart_top_drc_routed.rpx 2KB

rs485_uart_top_drc_opted.rpx 2KB

rs485_uart_top_bus_skew_routed.rpx 1KB

.vivado.begin.rst 227B

.write_bitstream.begin.rst 190B

.opt_design.begin.rst 190B

.route_design.begin.rst 190B

.place_design.begin.rst 190B

.init_design.begin.rst 190B

.vivado.end.rst 0B

.Vivado_Implementation.queue.rst 0B

.init_design.end.rst 0B

.write_bitstream.end.rst 0B

.opt_design.end.rst 0B

.route_design.end.rst 0B

.place_design.end.rst 0B

.vivado.end.rst 0B

.Vivado_Synthesis.queue.rst 0B

ISEWrap.sh 2KB

runme.sh 1KB

libps7.so 328KB

libremoteport.so 62KB

ps7_init.tcl 27KB

rs485_uart_top.tcl 6KB

rs485_uart_top.tcl 3KB

htr.txt 413B

htr.txt 405B

README.txt 130B

uart_recv.v 6KB

uart_send.v 5KB

rs485_uart_top.v 4KB

key_debounce.v 3KB

led_ctrl.v 2KB

rs485_uart_top.vdi 31KB

rs485_uart_top.vds 24KB

gui_handlers.wdf 20KB

java_command_handlers.wdf 6KB

synthesis.wdf 5KB

project.wdf 4KB

synthesis_details.wdf 100B

project.wpc 123B

rs485_uart_top_propImpl.xdc 2KB

top.xdc 708B

usage_statistics_webtalk.xml 53KB

webtalk_pa.xml 17KB

共 113 条

The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

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