VHDL编程练习-8位双向循环移位寄存器设计及仿真
199 浏览量
2023-10-25
23:36:33
上传
评论
收藏 569KB PDF 举报
H2.vhd:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H2 IS
PORT(CLK,LOAD,M,RESET: IN STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Q: OUT STD_lOGIC_VECTOR(7 DOWNTO 0));
END ENTITY H2;
ARCHITECTURE HBV OF H2 IS
BEGIN
PROCESS(CLK,RESET,M,LOAD)
VARIABLE Q1 : STD_lOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF RESET = '0' THEN --RESET
低
电
平
有
效
Q1 := (OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF LOAD = '1' THEN
资源评论
