Technical Note
DDR4 Point-to-Point Design Guide
Introduction
DDR4 memory systems are quite similar to DDR3 memory systems. However, there are
several noticeable and important changes required by DDR4 that directly affect the
board’s design:
• New V
PP
supply
• Removed V
REFDQ
reference input
• Changed I/O buffer interface from midpoint terminated SSTL to V
DD
terminated
pseudo open-drain (POD)
• Added ACT_n control
DDR4 added over 30 new features with a significant number of them offering improved
signaling or debug capabilities: CA parity, multipurpose register, programmable write
preamble, programmable read preamble, read preamble training, write CRC, read DBI,
write DBI, V
REFDQ
calibration, and per DRAM addressability. It is beyond the scope of
this document to provide an in-depth explanation of these features; however, a success-
ful DDR4 high-speed design will require the use of these new features and they should
not be overlooked. The Micron DDR4 data sheet provides in-depth explanation of these
features.
As the DRAM’s operating clock rates have steadily increased, doubling with each DDR
technology increment, DRAM training/calibration has gone from being a luxury in DDR
to being an absolute necessity with DDR4. For example, if the required V
REFDQ
calibra-
tion and data bus write training were not correctly performed, DDR4 timing specifica-
tions would have to be severely derated; but the issue is moot since the specifications
require V
REFDQ
calibration and data bus write training.
The first section of this document highlights some new DDR4 features that can help en-
able a successful board operation and debug. These features offer the potential for im-
proved system performance and increased bandwidth over DDR3 devices for system
designers who are able to properly design around the timing constraints introduced by
this technology. The second section outlines a set of board design rules, providing a
starting point for a board design. And the third section details the calculation process
for determining the portion of the total timing budget allotted to the board intercon-
nect. The intent is that board designers will use the first section to develop a set of gen-
eral rules and then, through simulation, verify their designs in the intended environ-
ment.
The suggestions provided in this technical note mitigating
t
RC,
t
RRD,
t
FAW,
t
CCD, and
t
WTR can help system designers optimize DDR4 for their memory subsystems. For sys-
tem designers who find the increases offered by DDR4 are not enough to provide relief
in their networking subsystems, Micron offers a comprehensive line of memory prod-
ucts specifically designed for the networking space. Contact your Micron representative
for more information on these products.
TN-40-40: DDR4 Point-to-Point Design Guide
Introduction
CCMTD-1725822587-10240
tn4040_ddr4_point_to_point_design_guide.pdf - Rev. H 08/2020 EN
1
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