Proposed DDR4 Full spec update(79-4C) Item No. 1716.7D
4.12 ZQ Calibration Commands ................................................................................................................................ 62
4.12.1 ZQ Calibration Description 62
4.13 DQ Vref Training ................................................................................................................................................ 63
4.13.1 Example scripts for VREFDQ Calibration Mode: 66
4.14 Per DRAM Addressability................................................................................................................................... 69
4.15 CAL Mode (CS_n to Command Address Latency)............................................................................................. 72
4.15.1 CAL Mode Description 72
4.15.2 Self Refresh Entry, Exit Timing with CAL 75
4.15.3 Power Down Entry, Exit Timing with CAL 75
4.16 CRC ................................................................................................................................................................... 76
4.16.1 CRC Polynomial and logic equation 76
4.16.2 CRC data bit mapping for x8 devices 78
4.16.3 CRC data bit mapping for x4 devices 78
4.16.4 CRC data bit mapping for x16 devices 78
4.16.5 Write CRC for x4, x8 and x16 devices 79
4.16.6 CRC Error Handling 79
4.16.7 CRC Frame format with BC4 80
4.16.8 Simultaneous DM and CRC Functionality 83
4.16.9 Simultaneous MPR Write, Per DRAM Addressability and CRC Functionality 83
4.17 Command Address Parity( CA Parity )............................................................................................................... 83
4.17.1 CA Parity Error Log Readout 89
4.18 Control Gear-down Mode................................................................................................................................... 90
4.19 DDR4 Key Core Timing...................................................................................................................................... 93
4.20 Programmable Preamble ................................................................................................................................... 96
4.20.1 Write Preamble 96
4.20.2 Read Preamble 98
4.20.3 Read Preamble Training 98
4.21 Postamble .......................................................................................................................................................... 99
4.21.1 Read Postamble 99
4.21.2 Write Postamble 99
4.22 ACTIVATE Command ........................................................................................................................................ 99
4.23 Precharge Command......................................................................................................................................... 99
4.24 Read Operation................................................................................................................................................ 100
4.24.1 READ Timing Definitions 100
4.24.1.1 READ Timing; Clock to Data Strobe relationship 104
4.24.1.2 READ Timing; Data Strobe to Data relationship 105
4.24.1.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation 106
4.24.1.4 tRPRE Calculation 108
4.24.1.5 tRPST Calculation 109
4.24.2 READ Burst Operation 110
4.24.3 Burst Read Operation followed by a Precharge 121
4.24.4 Burst Read Operation with Read DBI (Data Bus Inversion) 123
4.24.5 Burst Read Operation with Command/Address Parity 124
4.24.6 Read to Write with Write CRC 125
4.24.7 Read to Read with CS to CA Latency 126
4.25 Write Operation................................................................................................................................................ 127
4.25.1 Write Timing Parameters 127
4.25.2 Write Data Mask 128
4.25.3 tWPRE Calculation 129
4.25.4 tWPST Calculation 130
4.25.5 Write Burst Operation 131
4.25.6 Read and Write Command Interval 146
4.25.7 Write Timing Violations 147
4.25.7.1 Motivation 147
4.25.7.2 Data Setup and Hold Offset Violations 147
4.25.7.3 Strobe and Strobe to Clock Timing Violations 147
4.26 Refresh Command........................................................................................................................................... 147
4.27 Self refresh Operation...................................................................................................................................... 149
4.27.1 Low Power Auto Self Refresh 150
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