DDR4 SPD Jedec规范 V4
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Release 26
JEDEC Standard No. 21-C
Page 4.1.2.L-4 – 1
JESD 21-C Section Title: Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules
Committee Document Reference Title: DDR4 SPD Document Release 4
Device Type Identifier: UDIMM Revision 1.1
RDIMM Revision 1.2
LRDIMM Revision 1.2
NVDIMM-N Revision 1.1
1 Scope
This annex describes the serial presence detect (SPD) values for all DDR4 modules. The SPD data provides critical information about
all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the
system memory channels. The storage capacity of the SPD EEPROMs is limited, so a number of techniques are employed to optimize
the use of these bytes, including overlays and run length limited coding.
All unused entries will be coded as 0x00. All unused bits in defined bytes will be coded as 0 except where noted.
Timing parameters in the SPD represent the operation of the module including all DRAMs and support devices at the lowest
supported supply voltage (see SPD byte 11), and are valid from t
CKAVG
min to t
CKAVG
max (see SPD bytes 18 and 19).
To allow for maximum flexibility as devices evolve, SPD fields described in this document may support device configuration and
timing options that are not included in the JEDEC DDR4 SDRAM data sheet (JESD79-4). Please refer to DRAM supplier data sheets
or JESD79-4 to determine the compatibility of components.
2 History
Computer main memory buses have traditionally been defined by the generation of memory attached to the bus, e.g., EDO, SDRAM,
DDR1, etc. The bus interface protocol and characteristics have largely been defined by the memory type. Clock frequency, CAS
latencies, refresh recovery times and similar parameters defined the timing of signals between memory controller and the memory,
and parameters such as number of ranks installed and device widths allowed system software to determine the memory capacity and
similar high level characteristics of each module.
Over time, the memory bus has been extended to include additional features for application specific requirements. Registered
DIMMs, for example, increased total capacity by buffering the loading of the address bus signals, allowing more DRAM to be
installed. Similarly, Load Reduced DIMMs buffered the data bus as well, allowing even more ranks of memory to be supported. As
each new extension to the function of the memory bus was introduced, system software combined knowledge of those extensions
with information programmed into the EEPROM in the SPD to determine how to use and optimize the new features. Using the
RDIMM as an example, systems understood than an additional clock of latency needed to be added to the DRAM latency to
accommodate propagation delay through the register.
In later generations, the DRAM to host interface is completely virtualized. A memory module may have no DRAM at all, yet may use
the DRAM bus to communicate with the host by emulating the DRAM channel interface. These virtual interfaces must appear to the
system as one of the base module types, i.e., UDIMM, RDIMM, or LRDIMM. Modules that incorporate at least one non-DRAM
media type for the purpose of main memory data storage are called “hybrid”, they act like a DRAM but on the other side of the
interface protocol are some other memory type(s).
3 SPD Architecture
The SPD contents architecture must support the many variations of module types while remaining efficient. A system of overlay
information selected through the use of “key bytes”, or selectors for the type of information to load has been implemented. The
following DDR4 module SPD address map describes where the individual lookup table entries will be held in the serial EEPROM.
Consistent with the definition of DDR4 generation SPD devices (EE1004 and TSE2004) which have four individual write protection
blocks of 128 bytes in length each, the SPD contents are aligned with these blocks as shown in Table 1:
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