TN4040_DDR4_Point_to_Point_Design_Guide.pdf资源-CSDN文库

需积分: 9 26 浏览量 2019-01-17 20:02:04 上传评论 1 收藏 866KB PDF 举报

资源详情

资源评论

Technical Note

DDR4 Point-to-Point Design Guide

Introduction

DDR4 memory systems are quite similar to DDR3 memory systems. However, there are

several noticeable and important changes required by DDR4 that directly affect the

board’s design:

• New V

supply

• Removed V

REFDQ

reference input

• Changed I/O buffer interface from midpoint terminated SSTL to V

terminated

pseudo open-drain (POD)

• Added ACT_n control

DDR4 added over 30 new features with a significant number of them offering improved

signaling or debug capabilities: CA parity, multipurpose register, programmable write

preamble, programmable read preamble, read preamble training, write CRC, read DBI,

write DBI, V

REFDQ

calibration, and per DRAM addressability. It is beyond the scope of

this document to provide an in-depth explanation of these features; however, a success-

ful DDR4 high-speed design will require the use of these new features and they should

not be overlooked. The Micron DDR4 data sheet provides in-depth explanation of these

features.

As the DRAM’s operating clock rates have steadily increased, doubling with each DDR

technology increment, DRAM training/calibration has gone from being a luxury in DDR

to being an absolute necessity with DDR4. For example, if the required V

REFDQ

calibra-

tion and data bus write training were not correctly performed, DDR4 timing specifica-

tions would have to be severely derated; but the issue is moot since the specifications

require V

REFDQ

calibration and data bus write training.

The first section of this document highlights some new DDR4 features that can help en-

able a successful board operation and debug. These features offer the potential for im-

proved system performance and increased bandwidth over DDR3 devices for system

designers who are able to properly design around the timing constraints introduced by

this technology. The second section outlines a set of board design rules, providing a

starting point for a board design. And the third section details the calculation process

for determining the portion of the total timing budget allotted to the board intercon-

nect. The intent is that board designers will use the first section to develop a set of gen-

eral rules and then, through simulation, verify their designs in the intended environ-

ment.

The suggestions provided in this technical note mitigating

RC,

RRD,

FAW,

CCD, and

WTR can help system designers optimize DDR4 for their memory subsystems. For sys-

tem designers who find the increases offered by DDR4 are not enough to provide relief

in their networking subsystems, Micron offers a comprehensive line of memory prod-

ucts specifically designed for the networking space. Contact your Micron representative

for more information on these products.

TN-40-40: DDR4 Point-to-Point Design Guide

Introduction

CCMTD-1725822587-10240

tn4040_ddr4_point_to_point_design_guide.pdf - Rev. F 8/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. All

information discussed herein is provided on an "as is" basis, without warranties of any kind.

DDR4 Overview

DDR4 SDRAM is a high-speed dynamic random-access memory internally configured

as an 8-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8

configurations. The device uses an 8n-prefetch architecture to achieve high-speed oper-

ation. The 8n- prefetch architecture is combined with an interface designed to transfer

two data words per clock cycle at the I/O pins.

A single READ or WRITE operation consists of a single 8n-bit wide, four-clock data

transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-

cycle data transfers at the I/O pins.

This section describes the key features of DDR4, beginning with Table 1, which com-

pares the clock and data rates, density, burst length, and number of banks for the five

standard DRAM products offered by Micron.The maximum clock rate and minimum

data rate are the operating conditions with DLL enabled or normal operation.

Table 1: Micron's DRAM Products

Product

Clock Rate (

CK) Data Rate

Density

Prefetch

(Burst

Length)

Number

of BanksMax Min Min Max

SDRAM 10ns 5ns 100 Mb/s 200 Mb/s 64–512Mb 1n 4

DDR 10ns 5ns 200 Mb/s 400 Mb/s 256Mb–1Gb 2n 4

DDR2 5ns 2.5ns 400 Mb/s 800 Mb/s 512Mb–2Gb 4n 4, 8

DDR3 2.5ns 1.25ns 800 Mb/s 1600 Mb/s 1–8Gb 8n 8

DDR4 1.25ns 0.625ns 1600 Mb/s 3200 Mb/s 4–16Gb 8n 8, 16

Density

The JEDEC

standard for DDR4 SDRAM defines densities ranging from 2–16Gb; howev-

er, the industry started production for DDR4 at 4Gb density parts. These higher-density

devices enable system designers to take advantage of more available memory with the

same number of placements, which can help to increase the bandwidth or supported

feature set of a system. It can also enable designers to maintain the same density with

fewer placements, which helps to reduce costs.

Prefetch

As shown in Table 1, prefetch (burst length) doubled from one DRAM family to the next.

With DDR4, however, burst length remains the same as DDR3 (8). (Doubling the burst

length to 16 would result in a x16 device transferring 32 bytes of data on each access,

which is good for transferring large chunks of data but inefficient for transferring small-

er chunks of data.)

Like DDR3, DDR4 offers a burst chop 4 mode (BC4), which is a psuedo-burst length of

four. Write-to-read or read-to-write transitions get a small timing advantage from using

BC4 compared to data masking on the last four bits of a burst length of 8

(BL = 8) access; however, other access patterns do not gain any timing advantage from

this mode.

TN-40-40: DDR4 Point-to-Point Design Guide

DDR4 Overview

CCMTD-1725822587-10240

tn4040_ddr4_point_to_point_design_guide.pdf - Rev. F 8/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Parity Error Detection

Command/address (CA) parity takes the CA parity signal (PAR) input carrying the parity

bit for the generated address and command signals and matches it to the internally

generated parity from the captured address and command signals. High-level, parity er-

ror-detection functions include:

• CA parity provides parity checking of command and address buses: ACT_n, RAS_n,

CAS_n, WE_n and the address bus (Control signals CKE, ODT, CS_n are not checked)

• CA parity uses even parity; the parity bit is chosen so that the total number of 1s in

the transmitted signal—including the parity bit—is even

• The device generates a parity bit and compares with controller-sent parity; if parity is

not correct, the device flags an error, as shown in the Command/Address Parity Oper-

ation

• A parity error sets a flag using the ALERT_n signal (long low pulse; 48–144 clocks)

Figure 2: Command/Address Parity Operation

DRAM controller

Command/address

Even parity

GEN

Even parity bit

DRAM

Command/address

Even parity

GEN

Compare

parity

bit

Command/address

Data Bus Inversion

New to DDR4, the data bus inversion (DBI) feature enables these advantages:

• Supported on x8 and x16 configurations (x4 is not supported)

• Configuration is set per-byte: One DBI_n pin is for x8 configuration; UDBI_n, LDBI_n

pins for x16 configuration

• Shares a common pin with data mask (DM) and TDQS functions; Write DBI cannot be

enabled at the same time the DM function is enabled

• Inverts data bits

• Drives fewer bits LOW (maximum of half of the bits are driven LOW, including the

DBI_n pin)

• Consumes less power (power only consumed by bits that are driven LOW)

• Enables fewer bits switching, which results in less noise and a better data eye

• Applies to both READ and WRITE operations, which can be enabled separately (con-

trolled by MR5)

TN-40-40: DDR4 Point-to-Point Design Guide

DDR4 Overview

CCMTD-1725822587-10240

tn4040_ddr4_point_to_point_design_guide.pdf - Rev. F 8/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

剩余30页未读，继续阅读

评论收藏

内容反馈

TN4040_DDR4_Point_to_Point_Design_Guide.pdf

评论0

最新资源

TN4040_DDR4_Point_to_Point_Design_Guide.pdf

评论0

最新资源

相关推荐

DDR2、DDR3、DDR4、DDR5规范，此外还有测试指导、layout指导，硬件设计指导

tn4040_ddr4_point_to_point_design_guide.pdf

DDR4设计规范.doc

DDR4规范.pdf

DDR4 PCB设计规范&设计要点

三星DDR4选型-命名简介-规格参数一览表

DDR4 SDRAM UDIMM Design Specification-4_20_26R29.pdf

DDR4_SODIMM_Design_Specification_V100_20140701 DDR4协会规范

DDR4 SDRAM SO-DIMM Design Specification Revision 1.31 August 2019

DesignCon2019关于LPDDR5的资料

Hardware and Layout Design Considerations for DDR4 SDRAM.pdf

Cadence宣布业内首个DDR4 Design IP解决方案在28纳米级芯片上得到验证.pdf

Module 4.20.27.A Annex A, Raw Card A, in 288-Pin, 1.2 V (VDD), PC4-1600-PC4-1866-PC4-2133-PC4-2400-PC4-2666-PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification -完整英文电子版（24页）.pdf

Module 4.20.27.B Annex B, Raw Card B, in 288-Pin, 1.2 V (VDD), PC4-1600-PC4-1866-PC4-2133-PC4-2400-PC4-2666-PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification - 完整英文电子版（25页）.pdf

MODULE4.20.27.D - Annex D, R-C D, in 288-Pin, 1.2 V (VDD), PC4-1600-PC4-1866-PC4-2133-PC4-2400-PC4-2666-PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification - 完整英文电子版（31页）.pdf

Rockchip_Developer_Guide_Power_Analysis_CN.pdf

protected_ncverilog.rar_DRAM_ddr4_ddr4模型_ncverilog_silkei2

xilinx_DDR3_design_guide.rar_DDR3设计_ddr3_ddr3 fpga_xilinx FPGA D

Rockchip_RV1126_RV1109_Hardware_Design_Guide_V11_20200624_CN.pdf

16Gb_32Gb_x4_x8_3DS_DDR4_SDRAM_ddr_ddr4_

DDR4规范要求

DDR4接口标准

DDR4详细资料

DDR4 SDRAM STANDARD 规范

DDR4台式机内存条原理图.pdf

DDR3 to DDR4

designcon19-analyzing-lpddr4x-interfaces-cp.pdf

micron_lpddr4.pdf

JESD209-4B_Low Power Double Data Rate 4 (LPDDR4).pdf

ddr3_product_guide_oct_09